| Episodes | 312 |
| Mentions | 767 |
| Cited here | 86 |
| First — last | #2 — #723 |
| Top guests | Dave Vandenbout, Tim Ansell, Jeri Ellsworth |
| Related | microcontroller · analog to digital converter · asic · verilog · vhdl |
A field-programmable gate array (FPGA) is an integrated circuit whose logic function is fixed after manufacture by a configuration bitstream, in SRAM-based parts reloaded from external flash at every power-up.[286] Internally, the fabric consists of lookup tables, flip-flops, carry chains and a programmable routing network, supplemented by hard blocks such as multipliers, block RAM and, in modern devices, complete processor cores.[103][302][150] The device class occupies the space between software-programmable processors and application-specific integrated circuits: it offers concurrency and deterministic timing that no processor can match, at a substantial penalty in die area, unit price and power consumption relative to custom silicon.[103][254][264] FPGAs matter economically because mask-set costs on leading-edge processes exceed ten million dollars, which confines ASICs to ever-narrower high-volume bands and leaves reconfigurable fabric to cover everything else.[103]
Architecture
Logic fabric and routing
The primitive logic cell of an FPGA pairs a lookup table with a flip-flop and a carry chain, all present on every tile whether or not a given design uses them — a structural contrast with ASIC design, where each element is placed deliberately and a flip-flop costs six to eight times the area of an inverter.[616] The routing architecture, rather than the logic cell, is the dominant design decision in an FPGA, and the choices made in Xilinx’s 4000-series routing set the competitive position of its parts for more than fifteen years afterward.[103] Modern fabric provides no internal tri-state buffers, so the classic bidirectional microprocessor bus cannot be reproduced: an on-chip bus is built as two unidirectional buses, one from master to peripherals and one returning peripheral outputs through a multiplexer to the master.[467]
A coarse-grained reconfigurable architecture generalises the FPGA concept by making each primitive cell operate on whole words rather than single bits, so that one cell can execute an operation such as taking the absolute difference of two numbers and comparing it against a threshold.[374] An embedded FPGA, or eFPGA, is a block of such fabric instantiated as one core among many inside a larger system-on-chip, as distinct from a discrete part where the fabric is the whole device.[525] Complex programmable logic devices and older programmable logic parts use a fundamentally different fabric — a fixed product-term array rather than lookup tables and a routing network — which is why they differ from FPGAs in timing behaviour and configuration.[504]
Memory and hard arithmetic
FPGAs offer two kinds of on-chip memory: small amounts distributed within the logic cells, and dedicated block RAM that the designer instantiates explicitly; the split and the block sizes are vendor-specific, which makes memory structure one of the least portable parts of a design.[503] Fabric also carries hard arithmetic: current parts include dedicated blocks such as 36-bit multipliers settling in roughly three nanoseconds, so DSP throughput comes from purpose-built silicon inside the device rather than logic assembled from lookup tables.[302] Logic-cell counts are not directly comparable between vendors because the cells differ in how much logic each can absorb, so a capacity figure is only meaningful as a range or against a specific design.[525]
Configuration
SRAM-based FPGAs are volatile and reload their configuration from an external flash device at each power-up, which exposes the bitstream on the board and turns design security into a question of protecting that transfer rather than the chip alone.[286] Small families exist to remove those external dependencies: the Lattice MachXO integrates configuration flash, a voltage regulator and an oscillator on chip, eliminating the external configuration memory, extra supply rails and clock source that a conventional SRAM part requires.[224] Because the function lives in a reloadable bitstream, a contentious or licence-encumbered feature can be removed from an already-manufactured product without any hardware change and the same board resold with a different personality — Bunnie Huang used exactly this property to strip a disputed feature from a shipping design.[84]
History
Xilinx’s early product line ran from the 2000 series, which comprised two part numbers, through the 3000 series topped by the 3090, to the 4000 series, whose architecture was still being defined at the end of the 1980s with the lookup tables and flip-flops settled while the carry logic remained under argument.[103] Designs at that time were entered as schematics; Verilog reached FPGA design around the mid-1990s, arriving from custom silicon work where it was already established, and schematic entry has remained available in vendor tools ever since.[169] In the mid-1990s, entry into programmable logic cost thousands of dollars at minimum, with the design software alone running into thousands before any silicon, and cheap entry-level packages were deliberately made file-incompatible with the vendors’ professional tools so that a design begun in the low-cost environment had to be re-entered to move upward.[504]
The integration of hard intellectual property alongside fabric began in the early 2000s with the PowerPC embedded in the Xilinx Virtex-II Pro and the arrival of the MicroBlaze soft core, on the recognition that a large array of lookup tables alone had ceased to be enough.[452] Through the early 2000s the overwhelming majority of both Xilinx and Altera revenue came from telecommunications, with military and aerospace as secondary segments, which left the vendors directly exposed when the telecoms downturn followed the dot-com collapse.[452]
The FPGA market has long consisted of four established vendors: Altera, absorbed into Intel; Xilinx; Lattice; and Microsemi, formerly Actel, whose families include PolarFire.[419] Intel itself had made FPGAs in the early 1990s and exited, so its 2015 acquisition of Altera was a re-entry rather than a first move into programmable logic.[181][535] That acquisition reframed the FPGA from a general-purpose logic device into data-centre and data-processing infrastructure, and in doing so removed the prospective acquirers that smaller programmable-logic companies had been counting on.[535] Intel later moved its FPGA business back out as a separate entity, independent again while remaining tied to Intel’s foundry.[659] Altera’s naming illustrates how poorly family names track architecture: the Max brand, long associated with CPLDs such as the Max 3000, was reused for the Max 10 low-cost FPGA even though Max parts had used FPGA fabric internally for some time.[219]
Design entry and toolchains
Hardware description languages
Verilog and VHDL are among the few genuinely universal hardware standards: RTL written without vendor-specific IP blocks can be pushed through different vendors’ FPGA flows, and with care through an ASIC flow, unchanged.[650] Verilog is the more practical first language because the open-source tools favour it and most published cores and examples are written in it, while VHDL remains common but narrows the available toolchain.[467] Verilog is increasingly treated as the assembly language of the field — generated by higher-level Python-based tools such as MyHDL, Migen and LiteX, but still required for debugging what those generators emit.[469] Schematic entry survives in FPGA tools for a legitimate reason: consolidating discrete glue logic such as shift registers and flip-flops into one small device does not justify learning a hardware description language.[567]
Synthesis and vendor flows
Logic synthesis is a compiler in the same sense as a language compiler: it transforms an HDL description into whatever primitives the target provides, so an adder in source becomes a dedicated adder primitive on a coarse-grained array, a carry chain on an FPGA, or NAND and NOR gates in an ASIC flow.[374] Tcl is the scripting language that drives both FPGA and ASIC tool flows, so build automation in this domain means writing Tcl regardless of vendor.[721]
Vendor toolchains have historically shipped as a single monolithic install covering every supported device and board support package rather than downloading on demand, because one daily build of one package is easier for the vendor to manage than a hundred separately versioned downloads.[16] Vendors give away the tools for the bulk of the catalogue and charge only for support of the extreme high-end parts, on the reasoning that designers using five- and ten-thousand-dollar devices are not price-sensitive about tooling.[302] The dominant cost in learning such a flow is procedural rather than conceptual: Dave Vandenbout of Xess counted eighty pages of tutorial screenshots before a first LED blinked, because every dialogue in the flow has to be shown.[181] Altera once promoted a C-to-hardware flow in which the developer wrote C for a soft processor core inside the FPGA, then selected a routine and had the tool synthesise equivalent hardware for it, turning a subroutine call into a hardware accelerator.[317] Simulink blocksets similarly let a non-HDL engineer assemble a math model and emit VHDL or Verilog automatically, but the generated code is not maintainable as source, so the model rather than the HDL becomes the artefact under version control.[264]
One vendor, Efinix, departed from the Vivado and Quartus tool model by separating the fabric core from its periphery in an interface designer — a distinct piece of software that configures the I/O and anything attached to the core — on the reasoning that the periphery is what varies between customers.[535]
Open-source flows
The open-source flow is built around Yosys (a recursive acronym for the Yosys Open SYnthesis Suite) as the synthesis stage, completed by separate place-and-route and bitstream-packing tools.[449] The flow completes synthesis, place and route in around twenty seconds for a design whose vendor flow took about eight minutes, and that iteration speed changes how the tool is used rather than merely saving time.[449] The Lattice ECP5 evaluation board — one hundred dollars for 85,000 logic elements — was the largest FPGA with usable open-source tool support, making it the practical ceiling for open-toolchain work at the time.[423] The iCE40 toolchain is small enough to be hosted on a server or run inside a web browser, which collapses the path from plugging in a board to a blinking LED to a matter of minutes.[395] Open process design kits have since made it possible to fabricate an FPGA itself as an open design, with a University of Utah project targeting the SkyWater process.[501]
Soft processors and system-on-chip
The FPGA and the microcontroller converged from both directions: FPGAs gained hard silicon processors and peripherals, while microcontrollers gained small blocks of embedded programmable fabric, blurring the boundary between the two device classes.[102] All four major vendors reintroduced hard processor cores into their fabric, an admission that pure programmable logic was not displacing the processor and that customers wanted conventional sequential compute alongside it.[150] On a system-on-chip such as the Zynq, the hard peripheral set — USB, gigabit Ethernet, SDIO, UART, CAN, I2C and SPI — could all be implemented in fabric instead, so hardening those digital peripherals buys area and power rather than capability; the analogue-to-digital converters are the part that cannot be moved into fabric.[156]
Soft-core capacity is modest in fabric terms: a 32-bit RISC-V core fits in roughly half of a 5,000-logic-element iCE40 part, leaving the other half for custom peripherals.[423] The PicoRV32 occupies roughly 750 lookup tables on Xilinx 7-series fabric and trades instructions per cycle for very high clock frequency, which lets it share a clock domain with surrounding high-speed logic and avoid a clock-domain crossing.[374] A multi-core Linux-capable system-on-chip built from open RISC-V cores such as VexRiscv fits in about 35,000 lookup tables or fewer — mid-range rather than high-end fabric.[547] RISC-V displaced ad-hoc and legacy architectures as the default soft-core target because its compiler support in GCC, Clang and LLVM improved rapidly, which matters more than gate count when the core is handed to end users.[423] Architecture licensing shaped the earlier landscape: Intel treated the 8048 and 8051 as end-of-life standard products and tolerated hundreds of clones — the 8051 alone has been cloned by over 300 companies — while Motorola, Microchip and Atmel defended their cores, which is why open cores cluster around the former.[169]
A soft microcontroller in fabric can be given exactly the peripheral complement a design needs, including an arbitrary number of serial ports, and each port can be paired with dedicated logic that polls its sensor and deposits the result in a register, removing the periodic servicing that would otherwise consume processor time.[395] Even a soft core running at only about 20 MHz can outperform expectations because the hardware around it is malleable: rearranging eight bits scattered across eight registers so they sit in one register replaces sixteen read-and-mask instructions with a single read, an eightfold gain with no equivalent on fixed silicon.[703]
Wishbone is a standardised on-chip bus used inside FPGAs to attach custom peripherals to a soft CPU, and host-side bridges onto that bus let scripts on a development machine read and write the registers of peripherals inside the fabric; because the same register API is presented to a soft core running inside the part, a script developed on the host runs unchanged once the bridge is removed.[449][375] The bus’s external addressability also means a running program’s peripheral state can be altered directly rather than by patching its code.[449]
Selection against alternatives
Versus microcontrollers
The screening question for an FPGA is bandwidth and concurrency: human-interaction and other low-bandwidth tasks belong on a microcontroller, and fabric is justified only where there are genuinely parallel processes or hard latency requirements.[181] For a fixed function, a dedicated embedded processor will generally beat an FPGA on power consumption, which is why low-power claims from FPGA vendors are only meaningful relative to other FPGAs.[2] The task that cleanly separates the two is concurrent real-time observation: watching three lines toggling at 10 MHz and extracting a bit pattern on the fly is beyond any single processor and routine for a ten-dollar FPGA, while where a fifty-cent microcontroller suffices, the FPGA is the wrong tool.[103] Instantiating a soft CPU and running ordinary sequential code on it merely duplicates what a microcontroller already does, using none of the fabric’s advantages; the fabric earns its cost only where concurrency or determinism is required.[103] The rising capability of microcontrollers is what keeps FPGAs niche — each processor generation absorbs applications that would once have needed fabric — and the FPGAs present a steeper entry barrier as well, because nearly every electronics engineer already programs in C while hardware description languages demand an unfamiliar concurrent paradigm in which everything happens at once rather than line by line.[302][106][127]
Embedding general-purpose fabric in a microcontroller carries high area and power overhead and a steep learning curve, which is why the Raspberry Pi RP2040 instead provides programmable I/O blocks: stripped-down programmable state machines specialised to serial I/O at the cost of an ordinary serial peripheral, able to implement VGA, I2S, SD-card and DVI interfaces.[529] Such a block is not a small FPGA — it lacks a general routing fabric, so its logic is confined to the I/O pins it serves and cannot be arbitrarily interconnected.[595]
Versus ASICs
For a fixed function such as a turbo decoder, an ASIC implementation yields roughly a twenty-fold efficiency advantage or better over an FPGA; ASICs always win technically and lose only because the volume needed to amortise a spin is rarely there.[254] FPGAs displace ASICs not by being intrinsically better but because fabs move relentlessly to tighter geometries on larger wafers, driving mask-set cost for a leading-edge process past ten million dollars and shrinking the volume band in which an ASIC pays back.[103] Comparing the two on unit price alone is a mistake: die area, physical package size and above all power consumption also separate them, which is why FPGAs rarely reach consumer products even when the price gap closes.[264] A metallised gate array sits between the two — the base wafer is common and only the metal layers are customised — which cuts non-recurring engineering relative to a full mask set while removing the FPGA’s reconfigurability.[147]
Where a platform must track a moving workload, such as evolving machine-learning models, fabric lets the hardware change with a new bitstream instead of a new tape-out; the usual progression is to prototype and iterate in fabric and move to custom silicon only when both design and volume have settled.[519] Migrating a design to an ASIC forfeits reconfigurability, so a common mitigation is to embed a small soft processor core in the ASIC to handle housekeeping in otherwise idle intervals, keeping behaviour changeable in firmware rather than frozen in silicon — Jeri Ellsworth’s chip carried a small 6502 active during blanking periods for precisely this reason.[147]
Versus GPUs and CPLDs
For accelerated computing, a GPU carries a much lower upfront cost than an FPGA solution, so the FPGA route pays back only for workloads run long enough for its power and throughput advantage to dominate the initial outlay.[296] A CPLD is preferred over an FPGA where the design is small, pin count must be low, and timing must be predictable: FPGA routing is less deterministic than the CPLD’s fixed interconnect, even though the FPGA is far faster in absolute terms.[524]
Applications
Signal processing and instrumentation
The structural advantage of an FPGA over a processor is streaming: data can be processed as it arrives at full rate rather than buffered into a block and post-processed by iteration.[178] Even inexpensive FPGAs deliver very large speed-ups on applications that parallelise across a signal chain, such as video processing and simultaneous acquisition from many sensor inputs.[302] The standard architecture for a high-bandwidth sensor system puts an FPGA in front of the processor to detect features, parameterise them and emit a reduced data stream, so the processor only ever sees a bandwidth it can handle.[302] A sensor emitting a 1.5-gigabit-per-second serial stream is commonly deserialised by a small FPGA or CPLD placed next to it, converting the serial data into a parallel bus a processor can accept.[324]
Digital beamforming for phased-array radar and sonar — combining many antenna elements to steer a beam electronically — is a traditional application for top-end FPGAs costing around ten thousand dollars each.[115] In a software-defined radio, signal processing in fabric runs at very high sample rates using fixed-point integer arithmetic, which introduces small rounding errors that are invisible in most applications and significant in demanding ones.[381] Publishing the FPGA source for such a radio lets users insert their own processing into the signal path to obtain hardware acceleration, a capability distinct from the software API.[381] In an auto-ranging current meter, the range switch must complete before the burden voltage across the sense resistor browns out the device under test — a target jumping from microamps to an amp in under 100 microseconds forces a range decision in about a microsecond, which is why that logic sits in an FPGA rather than a microcontroller; the same instrument’s FPGA keeps two external analogue-to-digital converters in exact sample-time synchronisation, something difficult with a microcontroller.[527] Another instrument design reformats acquired data into audio streams in its FPGAs so that a processor’s well-supported serial audio interface can serve as a high-throughput 32-bit sample transport.[640] The low-cost software-defined instrument category as a whole is architecturally an FPGA behind an analogue front end, with the host software defining which instrument the box currently is.[396]
Prototyping and verification of ASICs
A design intended for custom silicon is normally proven first in an FPGA, so the residual risk in an ASIC programme is any block with no FPGA equivalent; high-speed serialisers are the usual gap, leaving properties such as trace-length tolerance untestable before tape-out.[147] ASIC verification uses hardware emulation boxes containing grids of high-end FPGAs that implement the chip under design, so the design runs at usable speed instead of being software-simulated, and processor verification departments run such implementations continuously for weeks because failures that appear only after days of running a particular program are unreachable in software simulation.[176][374] A tiled architecture can be verified in a part far smaller than the target chip by instantiating only a few tiles: four tiles of a sixteen-core design fitted in a modest FPGA and flushed out almost all the bugs before tape-out.[254] Custom chip programmes prototype each controller as an FPGA build exposing the PHY interface on FPGA pins, run on a commercial prototyping system whose daughter cards carry real PHYs and connectors — the Raspberry Pi RP1 was proven this way, since the ASIC PHY itself can only be simulated until first silicon.[648] In another accelerator project, the validated RTL was ported to an FPGA with wrappers mapping its I/O to the FPGA’s pins so the design could be exercised against real firmware during the nine months the ASIC spent at the fab, with area and target-frequency closure checked continuously rather than at the end.[721] A fabricated processor can even be brought up by using an FPGA to model the memory it executes from, counting retired instructions while sweeping core voltage to reveal the undervolted point at which enough of the design still functions.[616]
Security research
Games console security has been broken by wiring an FPGA directly to the DRAM lines and corrupting data as the CPU cache is flushed back to memory, an attack requiring logic fast and deterministic enough to act within the memory timing window.[303] Implementing a memory controller in fabric rather than using a fixed system-on-chip is what makes memory-attack research possible, since the access patterns that trigger a fault can be varied directly; this approach found new Rowhammer vulnerabilities in memories advertised as protected.[547] Commercial bus analysers are built to emit well-formed traffic, which makes them useless for security testing; building the analyser in fabric is what allows deliberately malformed packets, such as ones whose length field disagrees with the byte count, and decoding a proprietary bus in real time at line rate is not achievable in software, which forces the analyser into an FPGA.[318] A USB 3.0 man-in-the-middle probe likewise requires traffic passed through fabric at full SuperSpeed rate, which meant developing an open-source USB 3.0 device core in Verilog rather than using a hard controller.[318]
Data centres and infrastructure
Microsoft’s Project Catapult placed an FPGA in the network path of each Azure server so that all traffic passes from the processor through the fabric before reaching the network — initially doing nothing but pass data through, later reconfigured remotely for hardware acceleration — with reported speed-ups between ten and a thousand times depending on the task, typically in the low tens.[317] The attraction of FPGAs for large infrastructure operators is a software-style deployment cycle, a change reaching hardware worldwide in minutes rather than years, bought at a substantial silicon and power cost for the configurability itself.[501] Remotely reconfigurable fabric across a fleet carries fleet-wide risk: a faulty bitstream pushed to a hundred thousand servers fails everywhere at once, so the deployment discipline has to match that of firmware rather than application software.[317] The baseboard management controller in a server, conventionally a fixed ASIC, can be replaced by an FPGA carrying open-source cores and peripherals, making the management path inspectable and modifiable rather than an opaque piece of hard silicon with privileged access.[547]
Space and other domains
Radiation-induced upsets in an FPGA’s configuration can be cleared by reconfiguring the affected region, which turns a radiation-tolerance problem into a computer-architecture problem of detecting and recovering from bit flips rather than a physics problem; a radiation-tolerant computer can be built by instantiating redundant processor cores in one FPGA and voting on their outputs, so a corrupted core is outvoted, then reconfigured and reintroduced to the voting set.[497] In satellite design the split between processors and FPGAs follows the interface load: the platform avionics use mostly processors, while payloads carry many FPGAs because they must interface to numerous different high-speed interfaces.[679]
Other representative uses include optical and imaging systems, where sensors impose timing that a microcontroller could only meet with a substantially more powerful part and a real-time operating system;[588] a camera run in a one-bit serial mode in which the FPGA supplies the clock and receives a data bit plus frame and line sync pulses, fitting a full camera interface through two spare I/O pins;[473] synchronisation of distributed real-time installations by having each node’s FPGA run a free-running 48 MHz 64-bit counter as its master time base, reported over UDP so a central computer can profile each node’s clock rather than force lockstep;[521] a dedicated FPGA whose entire function is protocol translation to a display’s non-standard parallel bus, as in the Pebble smartwatch, where the part disappears from the bill of materials if a system-on-chip vendor integrates the same interface;[715] partitioning a system so that safety interlocks live in fixed FPGA logic in the backplane while all user code runs on the processor, keeping safety-critical behaviour outside the application programmer’s reach;[218] and respinning a board with an FPGA that replicates an end-of-life ASIC’s behaviour, turning an obsolescence problem into a bounded logic-design problem against the old part’s observable interface.[253] A modern small FPGA is sold as three capabilities in one device: general-purpose custom logic, a reconfigurable neural-network implementation, and low-latency data-path processing.[535] At the hobbyist extreme, the Fomu is an iCE40 UP5K board small enough to sit entirely inside a computer’s USB port with the fabric implementing the USB interface itself, and a roughly twenty-dollar Gowin 9K-class part holds a complete 1990s-era computer including an MS-DOS-capable emulator with HDMI output.[555][673]
Board-level implementation
Pin count, not logic capacity, is what pushes a design out of the low-cost families: on the USRP software-defined radio, Matt Ettus’s daughterboard interface consumed about 110 pins, so a second such slot would have needed 220 pins, difficult to obtain in a low-cost part.[101] Selection for a pin-limited design reduces to a parametric search sorted by pin count and then price, and frequently lands one generation behind the current family, since the newest family often has no part offering that pin count at the lower price point.[198] Whether a die is core-limited or pad-limited explains the product mix: a logic-rich part is core-limited, so its I/O pads come essentially free with the area already spent on fabric, and vendors long had little incentive to offer high-density parts in low pin-count packages.[272] Package availability, not silicon capability, is the long-standing barrier for small-scale users, because the established vendors have little reason to offer hand-solderable packages; new entrants targeting the low end are the usual source of accessible parts.[264] Small-package options are frequently feature-reduced rather than merely pin-reduced: the 32-pin QFN MachXO omits memory blocks and PLLs entirely, so a design needing either must move to the 100-pin package.[224] The fine-pitch BGA packages that hold the smallest capable FPGAs are specified for high-density interconnect processes — via-in-pad with 0.2 mm vias on a 0.1 mm drill, filled and plated — which puts prototype fabrication into the thousands of dollars.[395]
A large FPGA can require upwards of a hundred decoupling capacitors, the case that motivates scripted or automated capacitor placement in layout tools.[337] An FPGA drawing large current surges at power-up drives a bulk capacitance requirement distinct from the high-frequency decoupling needed during operation.[488] Power delivery changes character with device class: a low-end part drawing an amp or two is fed by an ordinary switching regulator, the next tier drawing thirty to fifty amps requires a multiphase regulator, and top-end accelerator parts reach around 250 amps.[566]
Length matching to a large FPGA has to account for two effects beyond trace length: propagation delay differs by layer, so skew must be computed per net from per-layer lengths, and the package itself contributes an on-die delay before the signal reaches the BGA ball.[469] Most FPGA I/O is interchangeable, which lets a layout engineer reassign pins to simplify routing, but some pins are fixed by function or bank, and a schematic handed to a separate layout engineer must flag which pins may not be swapped or the constraint is silently violated.[549] Unused I/O pins default to tri-state, which makes it safe to route signal traces across their unused pads under solder mask to escape a dense package — a technique that fails only if a user later drives those pins deliberately.[395] An FPGA’s internal input comparators can be combined with external passives to form an analogue-to-digital converter, removing a dedicated ADC from the bill of materials for undemanding measurements.[549]
Clock-domain crossing is hard to implement correctly by hand and produces subtle, intermittent failures, so it should be taken from a standard library primitive; awkward clock ratios such as 33 to 50 MHz make hand-rolled solutions worse.[469] A general-purpose FPGA carrier board reduces to an FPGA, a host interface, a memory socket and a mezzanine connector, with power supplies, a clock generator and a small supervisory microcontroller besides; application-specific analogue front ends then arrive as plug-in daughterboards.[198] A commercial reconfigurable I/O platform partitions its FPGA into fixed vendor IP for the bus interface and DRAM, a window for the user’s high-level code, and a second window for low-level logic that talks to the user’s circuit, with a module developer kit documenting the timing and mechanical constraints for that second window.[138] The NanoBoard system identified attached peripheral modules by one-wire serial number and automatically pulled in the corresponding FPGA IP, giving genuine plug-and-play at the level of hardware blocks.[593]
Economics and industry structure
The price of an FPGA tracks the sheer size of its die rather than any premium for programmability; per unit of silicon delivered, FPGAs are not priced differently from other chips, and gross margins at Xilinx and Intel sat within a few percent of each other.[103] For roughly 95 percent of designs likely to end up in an FPGA, a design working on one vendor’s part can be made to work on another’s; vendor lock-in comes from tools, IP blocks and habit rather than from the fabric itself.[103] Vendor IP cores bundled with a toolchain win on economics rather than merit: building the equivalent from open sources is roughly twice the work, so open alternatives displace them only where they are already good enough to use unchanged.[547]
New FPGA companies have historically mostly failed, because competing with the incumbents requires simultaneously matching silicon, toolchain and IP ecosystem; entrants that survive do so by opening a segment the incumbents do not serve rather than competing head-on.[264] Efinix, founded in late 2012 by former Altera engineers, initially judged a full FPGA business impossible to build from scratch and planned instead to develop the technology, license it, and be acquired; a team of under ten people produced the software and early prototypes before the company shifted to selling its own products from 2017.[535] The market splits by power envelope: data-centre parts demand the newest process nodes, where mask sets alone cost millions, so only the largest vendors compete there, while edge and battery-powered applications are served by lower-density, low-power fabrics on older nodes.[525] Chinese vendors have opened the bottom of the market: a part with 1,152 lookup tables, 864 flip-flops and 72 kilobits of block SRAM appeared on complete five-dollar development boards, and low-cost instrument makers have moved from Xilinx Artix-7-class parts to substantially cheaper Chinese FPGAs to reach price points the established vendors cannot match.[464][710]
In low-volume products, engineering time dominates bill-of-materials cost, so designers will accept a three-hundred-dollar FPGA and its vendor reference design rather than spend weeks optimising down to a cheaper part.[64] The bet that all designs would move inside FPGAs failed on cost and power, with the exception proving the rule: the customers for whom the modular FPGA approach worked were makers of low-volume, high-value products such as medical devices, where non-recurring engineering dominates unit cost; the four-thousand-dollar development platform built on that bet did not sell, while a roughly three-hundred-dollar successor did.[593] Packaging an FPGA as a chiplet adds a layer of post-fabrication customisability inside a multi-die package, letting a custom part combine RF, power and fixed-logic dies with a region that remains reprogrammable for years.[499]
Working with the technology
The reliable way into FPGA work is to buy a development board with a working example, get that example running, and then work backwards into how the configuration and toolchain actually operate.[141] Learning to simulate before targeting hardware is standard advice for beginners, with Icarus Verilog and Verilator as the open-source simulators in common use.[467] A first FPGA project should be something a microcontroller cannot do easily — heavily parallel work, real-time serial decoding, or building a processor from scratch — since blinking an LED demonstrates nothing about the fabric and running a vendor demo is worthwhile only as toolchain familiarisation.[419] The parallel nature of logic in an FPGA, where everything happens at once, is harder to internalise than sequential line-by-line execution, and the difficulty is compounded because most engineers arrive with prior sequential programming experience to unlearn.[127]
Custom logic written into an FPGA comes with no datasheet: the designer builds on blocks nobody has documented, a real cost in maintenance and in consulting work where the time is hard to bill.[601] Putting an FPGA in a product to allow later fixes in HDL only pays off if the deployed units can actually be updated; without a working field-update path the reconfigurability is cost without benefit.[337] Where the end user is expected to modify the fabric, the vendor choice is dictated by the toolchain the user already knows rather than by the silicon — Ettus shipped Xilinx parts in the USRP for exactly this reason — while a closed product whose fabric the customer never touches leaves the designer free to pick on price and pinout.[101] Conversely, Michael Ossmann’s wideband software-defined radio designed to run from a USB 2.0 port met its cost and power budget by omitting the FPGA entirely: a small CPLD provides glue logic such as unsigned-to-signed conversion, and an ARM Cortex-M4 with DSP instructions does the processing.[214] A radio-astronomy and phased-array radar group fielding systems on a twelve-to-eighteen-month cycle, Greg Charvat’s group, adopted an unofficial policy of no longer using FPGAs because the development and debug time the fabric demands does not fit that schedule.[214] One hundred-megabit Ethernet cannot be probed directly with an oscilloscope because the line encoding makes traffic indistinguishable from noise; the practical instrument is an Ethernet PHY providing a data-valid signal followed by a small FPGA that parallelises the data into a scope’s parallel bus for decoding.[412]
Authenticating a product by having its FPGA bitstream challenge the host is defeated by users writing a substitute bitstream that implements the protocol, so a device whose configuration is loaded at run time cannot root its authentication in that configuration — the Garrison brothers’ analyser company discovered users doing exactly this.[237] Porting an existing processor design into an FPGA reproduces only the digital side: analogue pin functions and other mixed-signal blocks have no equivalent in most fabrics, so an open-sourced chip cannot simply be re-instantiated whole.[219] The ability to reconfigure fabric and push field updates erodes the ASIC discipline of proving architecture and test coverage before committing masks, since a mistake no longer has to be right the first time.[619] For bit-level workloads such as password cracking, which consist of XOR and shuffling operations needing no 32-bit arithmetic, the fabric of a Zynq outperformed a dedicated many-core floating-point processor on the same board, and contrary to the reputation for high power draw, an FPGA can be orders of magnitude more computationally efficient than a CPU or GPU for a suitable workload because the algorithm itself is laid out in parallel rather than replicated across cores that still execute sequentially.[254][466]