| Episodes | 40 |
| Mentions | 64 |
| Cited here | 31 |
| First — last | #17 — #722 |
| Top guests | Bunnie Huang, Tim Ansell, Steve Liebson |
| Related | fpga · transistor · microcontroller · semiconductor fab · silicon |
Moore’s Law is the observation that the density of integrated circuits — the amount of silicon function that fits in a given area at a given price — doubles on a regular cadence, commonly stated as every 18 months.[17][550] The statement concerns transistor density and cost, not processor speed, and the speed reading is a common misquotation.[17][550] The trend has functioned less as a physical law than as a self-fulfilling prophecy sustained by competitive pressure: each manufacturer invests to keep the doubling on schedule because a competitor otherwise will.[41][99] As scaling has slowed, the industry’s response has shifted toward parallelism, die stacking, and chiplet-based heterogeneous integration.[297][499][704]
Statement of the law
The trend is usually quoted as a doubling every 18 months, though formulations of 18 to 24 months also circulate; its author co-founded the company named for integrated electronics that produced the first single-chip microprocessor.[17][497] The underlying statement is about how much silicon function fits in the same area at the same price, not about how fast a chip runs.[17][550]
Two readings of the law are in common use: a lithographic reading, under which features shrink and transistor counts double, and a macro reading, under which memory halves in price and doubles in capacity every nine to eighteen months; whether the law is considered “over” depends on which definition is applied.[297] Under the density reading, the manufacturer chooses how to spend each generation’s surplus: more speed, lower power consumption for battery life, or more dies per wafer delivering the same function.[550]
Plotting the transistor counts of released processors against the predicted doubling line shows the actual data oscillating ahead of and behind the trend rather than tracking it smoothly.[484]
Historical development
Digital logic was built in bipolar technology until around 1980; bipolar was abandoned not because it stopped getting faster but because its power dissipation became intolerable, which drove the industry-wide switch to CMOS.[99] Companies that bet on gallium arsenide for speed lost out when CMOS became fast enough, a recurring pattern in which the incumbent process outruns an exotic alternative.[99]
Through the 1990s, clock frequency was the headline competitive axis in the megahertz and gigahertz races.[501] That axis ended well before density scaling did: desktop processors sat near three gigahertz for over a decade, and core count replaced frequency as the marketed specification.[61][501]
Using the chessboard-and-rice doubling parable as a yardstick, the counted generations of technology doubling passed the 32nd square around 2006, the point at which an exponential progression becomes visibly overwhelming.[195]
Forecasts of the end
Predictions of the law’s breakdown have a long history. One widely circulated forecast placed the breakdown of transistor scaling in the 2020 to 2030 window.[61] An IBM semiconductor research leader estimated on a Design Automation Conference panel that conventional semiconductor technology had about two more decades of runway.[99] Around eight-nanometer device dimensions, CMOS has been expected to require a fundamentally different approach — a boundary that had been predicted for roughly a decade without arriving.[228] GlobalFoundries’ decision to halt seven-nanometer development was a single-company capability decision rather than an industry ceiling, since TSMC continued developing that node.[406]
Extrapolating exponential doubling to the physical limit of one bit per atom yields an absolute ceiling of roughly 600 years, beyond which all reachable matter would be consumed as storage.[23]
Economic character
The doubling cadence is driven by commercial survival rather than technical enthusiasm. Fabs pursue each process generation under competitive pressure: if one company does not advance the node, a competitor will, which is why the whole industry marches in step.[41][564] The trend functions as a self-fulfilling prophecy in which each company invests to keep it on schedule because a rival otherwise will.[99] CMOS scaling continues because demand for storage, processing, and lower power funds it; without that economic pull, the technical progress would stop regardless of what physics permits.[228]
The industry has largely moved to a fabless-plus-foundry structure, with Intel the prime remaining example of a vertically integrated device manufacturer.[99] At the 28- and 20-nanometer generations, the process physics became severe enough that EDA tool selection could no longer be separated from the choice of foundry, forcing collaborative development and heavy mathematical modeling.[99]
Large corporations pipeline product development around the process cadence, so each year’s product is far enough along that an individual builder cannot match it.[61] As the density curve flattened, a counterpart cost curve moved the opposite way, with semiconductor development cost rising as dimensions shrink.[553] Only about two or three companies worldwide can run five- and three-nanometer CMOS processes — TSMC and Samsung, with Intel potentially reaching them.[553] Proprietary process design kits carry legal overhead measured in 800-dollar-per-hour lawyer time, so only ideas a team is already confident in get explored; open PDKs lower the barrier to trying speculative architectures.[501]
Falling digital electronics cost also reset pricing in adjacent markets: an entry-level benchtop oscilloscope sat near 800 dollars for decades until Rigol halved the 1052E’s price to 400 dollars in 2009.[293]
Physical and design constraints
Below the wavelength limit of deep-ultraviolet lithography, a single layer is decomposed into several coarser patterns exposed on top of one another to reach the fine resolution, a technique called multiple patterning.[553] Multiple patterning removes layout freedom that older nodes allowed: gates can no longer be placed at arbitrary orientations, and everything on a layer must run in the same direction.[553]
Bond pads do not shrink at anything like the rate transistors do, so on advanced nodes a small die becomes pad-limited rather than transistor-limited.[272] Modern node names are marketing labels rather than feature sizes: a so-called two-nanometer node contains no two-nanometer features, and physics limits real dimensions to roughly ten or eleven nanometers.[704]
Power is a parallel constraint. Efficiency was historically bought by lowering supply rails alongside parallelization, but rail voltages have approached diode-drop levels, removing that lever.[704] Packing more transistors into a small area raises power density and makes heat extraction a serious limit, and adding cores only helps if memory bandwidth can feed them.[501] Current compute scaling is limited by power and by DRAM cost rather than by lithography alone, pushing gains toward efficiency instead of raw capability.[722]
High-speed RF parts are typically not built on leading-edge CMOS at all but on silicon-germanium BiCMOS, where SiGe bipolar devices provide higher breakdown voltage for power handling and the on-die CMOS is a far older node used as a helper.[553]
Slowdown and its consequences
Transistor count per chip has kept roughly doubling, but what changed is how the transistors are usable: single-threaded performance hit a ceiling and core counts rose instead.[501] After roughly 40 years of hard scaling, present-day improvements come from more parallel processing rather than smaller transistors, and no successor technology with comparable breadth of application has emerged.[704]
System performance and transistor scaling are separable: architectural techniques such as parallelism can deliver performance gains that run ahead of the process-scaling schedule.[17] A common design habit, however, has been to accept slow compute-heavy tools on the assumption that future process generations will make them fast enough, deferring optimization work indefinitely.[19] The historical default answer to a performance shortfall was to wait roughly 18 months for faster silicon; when that stops working, the remaining lever is spending engineering time optimizing code or turning it into dedicated hardware.[317] ASIC design methodology has not been rethought at hundred-fold scale increments the way software practice has; chips are still designed with late-1990s methods because process scaling supplied the speed gains instead.[501]
If hardware performance stays flat for years, multi-year investments in optimizing compilers and hand-coded assembly start paying off because the gains are not erased by the next chip.[84] Physics makes the slowdown of transistor scaling essentially inevitable, and longer cycle times give architectural ideas more room to prove viability; under a fast cadence, by contrast, innovation is compressed into a window of months, because a full-stack idea must show a compelling improvement before the next node makes it irrelevant.[84] Backward compatibility combined with steady process gains makes incremental speedups the rational business choice, which suppresses architectural risk-taking such as moving the processor next to the memory.[84]
When scaling stops, memory capacity per generation stops multiplying, removing the yearly specification jump manufacturers had relied on for new product cycles.[61] A better strategy for a small hardware business than waiting for scaling to stall is to target niches large corporations serve badly.[61] Correspondingly, the end of easy gains in general-purpose computing opens more silicon niches, making specialized chip startups more viable than during the era of uniform scaling.[672]
Stacking and chiplets
When a process node runs out of headroom, effort shifts to packaging improvements until packaging itself becomes the limiting factor and a new node jump is made.[84] Once density gains in the plane stall, the industry response is vertical stacking of die — the same move a densely populated area makes when land runs out.[297] Chiplet and heterogeneous system integration is positioned as the successor enabler for semiconductor innovation as monolithic scaling reaches its end.[499]
Integrating everything onto one monolithic die remains the performance-optimal answer, providing roughly 13 metal layers, hundred-nanometer wire pitches, and the best energy efficiency, cost, and bandwidth; the trade is that monolithic integration abandons modularity entirely, producing a statically compiled blob with no reuse, whereas chiplets give hardware the equivalent of software libraries and linking.[650]
Custom and reconfigurable logic
Process headroom running out revived interest in programmable logic, restoring the long-standing tradeoff between FPGA custom logic and brute-force parallel processors.[296] Slowing process gains likewise increased interest in open-source FPGA toolchains, because optimizing custom logic becomes worthwhile when free performance no longer arrives.[421] FPGAs offer software-style deployment timescales — worldwide in minutes rather than years — but pay a substantial silicon cost for that configurability.[501]
Commodity ARM cores driven by smartphone volume became powerful enough that custom hardware such as FPGAs stopped being necessary for many embedded control applications.[105] Analog preprocessing before conversion retains real niches at low power, low amplitude, and low sensitivity, but analog will not match digital scaling for integration, complexity, and processing throughput.[119]
The long-run trend in the cost of compute is downward toward zero, now driven by GPUs, TPUs, and algorithmic efficiency rather than transistor scaling alone, letting models that once needed a cluster run on local machines.[626] Very large scale integration also remains the enabling substrate in its own right: modern phased arrays are practical because integration supplies the many data converters and wide data pipes that mechanically scanned radar could not.[729]