| Episodes | 77 |
| Mentions | 143 |
| Cited here | 28 |
| First — last | #31 — #722 |
| Top guests | Claire Wolf, Dave Vandenbout, Dmitry Nedospasov |
| Related | vhdl · fpga · hardware description language · risc v · asic |
Verilog is a hardware description language (HDL) used to describe digital electronic circuits at the register-transfer and structural levels, and it forms the basis of much digital chip design and verification work.[152] A single body of generic Verilog can serve two very different back ends: the same source is either synthesised against an ASIC standard-cell library or mapped onto the resources of an FPGA, which is what makes FPGA prototyping of an ASIC practical.[254] Beyond its role as a source language, Verilog functions as an interchange format: synthesis output is emitted as Verilog again, and many commercial place-and-route tools accept only strict structural subsets of the language as input.[374] Newer hardware description languages plug into existing flows precisely by emitting Verilog as their output.[672][469]
History and position among design-entry methods
Before hardware description languages reached programmable logic, designs were entered either as schematics or in proprietary notations such as AHDL and CUPL; those notations were Boolean descriptions rather than synthesis languages, performing logic expansion and minimisation while leaving the designer to understand the target primitives and carry out most of the structural work.[169] Schematic entry remains a workable first step into programmable logic, with Verilog modules as the second step, but it does not scale: a complicated piece of hardware cannot be built purely by drawing.[395] For custom silicon, schematic capture breaks down at roughly twenty to thirty standard cells and becomes unmanageable by about fifty, whereas a sixteen-bit register is a single declaration in an HDL and adding two registers is one expression rather than dozens of drawn NAND gates and carry logic.[672]
C-to-hardware compilation was tried as a commercial product line: a purchased compiler emitted VHDL or Verilog and drove the Xilinx and Altera flows in the background, so the user never handled the generated HDL; it worked for modest designs but not for high-end projects.[555] In current industry practice, digital design and verification remain heavily Verilog-based, with movement toward higher-level languages including SystemVerilog and SystemC.[152]
Semantics and mental model
Verilog and SystemVerilog are language representations of how logic gates are connected, not programs.[721] The source is a description of how to wire up hardware, and control logic is conventionally expressed as a state machine using well-established coding patterns.[395] The characteristic beginner failure in Verilog and VHDL is writing the description as though it executed sequentially: an FPGA has no pre-built sequential execution model, so every statement takes effect at once unless the designer has explicitly built a processor into the fabric to run sequential code.[181] Verilog’s C-like syntax actively worsens this failure for programmers arriving from software, because the resemblance suggests a program where none exists; drawing a schematic of gates is in a real sense closer to the silicon.[616]
The semantic gap between Verilog and VHDL is small enough that knowing one makes the other learnable; the genuine difficulty in either language is the parallel model, and a designer who does not hold a mental model of circuitry operating concurrently cannot write either language successfully.[181] The fundamental semantic difference between the two languages is the delta cycle, the model of how concurrent processes interact and settle during a simulation time step; Verilog implements it differently from VHDL, and internalising the model sharply reduces the error rate in written code.[237] Code written without that understanding fails until every conceivable case has been test-benched, whereas code written with it in mind frequently works before the first test bench exists.[237]
A practical way to build the association between HDL source and generated hardware is to compile small fragments deliberately and inspect them in the tool’s RTL viewer, which displays the gates the code produced, before moving to more abstract coding styles.[181]
Language choice in hardware description follows a geographic rather than a technical pattern: Verilog predominates on the United States west coast and in Asia, while VHDL predominates east of the Mississippi through to Europe, and military work is largely VHDL.[181] The verbosity difference between the two is large and visible: in textbooks printing equivalent implementations on facing pages, the Verilog page is mostly white space while the VHDL page fills entirely, Verilog requiring markedly less syntax and boilerplate for the same design.[303] That terseness has a cost: where VHDL requires a name to be declared in several places and cross-checks them, a Verilog typo in a signal name causes the synthesis tool to silently create an additional variable and continue, emitting only a warning rather than an error.[449]
Synthesis and the design flow
Inference is what makes an HDL worth using at a higher level of abstraction: Verilog and VHDL can infer RAMs and other structures from loops in the source, and a designer working with the right macros and abstractions can express an entire microcontroller in a couple of hundred lines that another engineer can read and recognise as a processor.[181] Most Verilog is generic, and the synthesis tool translates it into device-specific primitives on its own; only where the tool cannot perform the mapping does the designer instantiate vendor primitives by hand.[467]
The digital portion of a mixed-signal ASIC follows the same sequence as an FPGA design with one substitution: the Verilog is written and exercised in a test bench, then synthesised against standard cells such as two- and four-input AND gates and various flip-flops rather than lookup tables; synthesis emits a gate-level Verilog netlist, which is then placed, routed and closed on timing.[579] Coarse-grained target architectures complicate synthesis because the mapping is no longer one-to-many: an ordinary operator in source normally expands into many fine-grained cells, but a coarse-grained primitive requires the tool to recognise a whole constellation of operators and collapse it onto the single hardware primitive that implements it.[374] On the open-source side, Claire Wolf’s position was that designing for a novel architecture does not require a new domain-specific language: accepting a subset of ordinary Verilog and inferring the target primitives from it gives the same expressive power while keeping the existing language, tooling and knowledge base.[374]
Verilog has modules but no library mechanism in the software sense, and the available third-party IP is often commercial and not modular enough to include at will, so common infrastructure such as an AXI master or slave tends to be rewritten rather than imported.[469]
Verification
The working assumption in Verilog development is that the first version will be wrong, and the test bench is written on that assumption, applying an input to the simulated logic, reading the output and comparing it against an expected value.[721] The risk in carrying an HDL design from simulation into a metallised gate array is absorbed by the test benches written before commit, and test benches written for one target’s tools transfer to another target’s tools only partially.[147] A digital design taken to silicon is comparatively low-risk when the clock is not being pushed to the limit and the test benches on the Verilog have been done properly; the residual uncertainty in a mixed-signal part sits on the analogue side, where device behaviour depends on doping and process rather than on simulated logic.[201]
VHDL supports a stronger verification story than Verilog, extending to formal proofs that hardware behaves as specified, and Verilog’s syntax makes the same techniques harder to apply; a mixed-language practice follows, in which teams write the design itself in Verilog and the test benches in VHDL.[303]
Hand-written test benches are bounded by the imagination of their author and cannot reach all corner cases of a design with many input combinations. Verilator, a Verilog simulator that presents the design as a C wrapper, lets a harness written in C or C++ sweep the entire input space and check every output in minutes, making exhaustive simulation preferable to directed stimulus where the state space allows.[467] Test benches need not be written in an HDL at all: open-source simulators are commonly wrapped so that stimulus and checking are written in Python, the arrangement used for Tiny Tapeout submissions, and Verilog paired with a cocotb test bench is well suited to machine assistance for large reproducible interface blocks such as DDR controllers, while analogue schematic work and power net layout remain manual.[721][722]
Logical equivalence checking connects the two representations of a chip, taking the Verilog and the gate-level netlist and reporting whether they are logically identical, which is necessary because the correspondence between the two is not obvious to a human reader.[687] Formal equivalence checking can also validate a reverse-engineered toolchain: bitstreams generated from known designs were converted back into Verilog, and formal verification proved the extracted Verilog logically equivalent to the original input, replacing a large number of directed test cases with a proof over the important points.[374]
Pre-silicon security work on a chip starts with Verilog code review, because synthesis makes assumptions about the source; the assumptions found in review become concrete test cases, some confirmable pre-silicon and others deferred to post-silicon tests.[346] Silicon vendors retain the RTL simulation environment for shipped parts, so an application engineer can have a Verilog simulation of a peripheral re-run internally to confirm a suspected hardware defect such as a DMA trigger that does not fire.[511]
Portability and vendor constructs
Inferring a memory in Verilog by declaring an array and coding around it is hazardous for any design that may move: the inference is specific to the target’s memory blocks and breaks when the design is retargeted to a metallised gate array, a custom ASIC, or another FPGA vendor; the mitigation is to place a generic memory interface wrapper around every such block so nothing is inferred directly into the design.[173] Hand-instantiated primitives are what break portability in the other direction: moving a design from an iCE40 to an ECP5 came down to replacing the block RAM primitives with the equivalents for the new family.[467] On-chip block RAMs are small and vendor-specific, on the order of four to sixteen kilobits apiece, which is why memory is the resource most often instantiated explicitly rather than inferred.[467]
A downloadable Verilog soft core can be dropped straight into either vendor’s tool and run out of the box, but adapting it to the target usually means changing its memory model: an 8051 core written for external asynchronous RAM and EEPROM was retargeted to the FPGA’s own synchronous block memories so no external memory was needed.[169]
Soft processors and parameterisation
PicoRV32 is a RISC-V core written in pure Verilog and formally verified, properties that underpin its wide reuse as a drop-in soft processor.[467] A working RISC-V core has been published as roughly one hundred lines of Verilog, or about two hundred with reasonable formatting and comments, and demonstrated driving an LED matrix, which sets a lower bound on the source required for a minimal soft processor.[644]
Parameterisation in Verilog is literal rather than notional: a single parameter naming a CPU count actually determines how many processor cores are instantiated in the fabric, so raising it by one adds a core; the practical ceiling is resources and shared bandwidth, since the build fails when the part runs out of space and, above a certain count, the memory bus becomes so constrained that the cores wait on each other.[467]
Wishbone is a standardised on-chip bus used to attach peripherals written in Verilog to a soft CPU core inside an FPGA; because the bus is addressable from outside, a host connected over USB can write memory locations on it directly, altering a running program’s peripheral state without touching the program.[449] AXI, the ARM-derived bus used widely in Xilinx FPGA designs, is a complicated protocol with many details that must be got right; implementing an AXI interface in raw Verilog means writing all that logic and then verifying it against a vendor-supplied bus verification model that probes the design in a test bench.[469]
Open-source toolchains
A vendor FPGA toolchain is assembled from separable pieces rather than being monolithic: one supplier bundled Mentor Graphics Precision RTL for synthesis with its own proprietary place-and-route and deliberately bundled no simulator, on the basis that any Verilog simulator would work.[525] The open-source equivalent decomposes the same way, with SymbiFlow covering simulation, Yosys for synthesis, VPR for place and route and a final bitstream generation step.[525] The open-source iCE40 toolchain is a small, command-line-oriented install, in contrast to the Xilinx and Intel vendor toolchains that run to around sixty gigabytes.[644]
On a small part such as the iCE40 1K, which carries roughly a thousand logic cells with a lookup table and flip-flop apiece, an optimised open-source flow can go from Verilog to bitstream in under a second; on large designs the same flow is slower than the vendor tools, so the optimisation target is explicitly the small design.[374] Sub-second turnaround changes who benefits rather than how much time is saved: an experienced engineer spends most of the working day simulating individual cores and rarely synthesises the whole design, since a full synthesis may take a day, whereas beginners and workshop participants iterate by making a small change and observing the result in hardware immediately.[374] Retargeting the open-source synthesis tool to a new architecture is done by writing small Verilog snippets describing the target’s cells, so the language knowledge required to extend the tool is no more than that required to use it.[374]
For custom silicon, Qflow, built on Magic and a set of related packages, carries a design from Verilog synthesis through to mask generation, and a ring oscillator and a serial receiver have both been taken through it.[390] OpenLane, whose core is the separately developed OpenROAD project, accepts a hardware description language such as Verilog or VHDL at one end and handles the digital side, including IO routing, automatically.[616]
Higher-level languages and generation
Chisel is a hardware description language built as a domain-specific language inside Scala, chosen because Scala is strongly typed without the verbosity of VHDL and flexible enough to host a language of its own; like the Python-based generators, it emits Verilog or VHDL, so its output feeds the existing vendor tool flow unchanged.[469] Hosting a hardware description language inside a general-purpose programming language gives a meta layer: loops and conditionals in the host language run at elaboration time, so instead of describing one specific bus slave the designer writes a subroutine that generates the slave from parameters; the VexRiscv core is built this way, emitting a different CPU depending on whether a memory management unit, floating point or vector support is switched on.[469] Newer languages such as Amaranth are viable for open-source silicon and FPGA work specifically because they emit Verilog; producing Verilog is the compatibility requirement that lets any new language plug into the existing open-source flow.[672]
Chip configuration can itself be script-generated: on the Raspberry Pi RP1, a set of scripts consumes a configuration file and writes out the Verilog describing the part, so producing a variant with different clocks, GPIO counts and fabric means editing the configuration and re-running the scripts rather than editing RTL.[648] For algorithms still being explored, writing in C is often preferable to writing in Verilog even when the target is programmable logic, because the iteration cycle is much faster; this is why engineers arriving from the DSP processor world resist implementing signal processing directly in FPGA logic.[254]
Design practice
A digital design starts on paper, not in an editor: the target’s constraints, such as the number of pins available and the frequency those pins can run at, fix the IO interface and the target internal frequency, since there is no benefit in clocking internal logic faster than data can be fed in.[721] Meeting timing is set by device utilisation as much as by clock rate: a heavily utilised FPGA design whose core ran at 100 MHz, with filtering and sampling paths at 200 MHz and minor components near 40 MHz, took a long period of optimisation to close, and 200 MHz in a fully loaded part is hard even though the number sounds unremarkable.[237] Reducing the number of independent clock domains simplifies a design: an early version that fitted only two channels used unrelated clocks joined by glue FIFOs, whereas the reworked design related all its clocks and left only the USB 3.0 bridge interface, a 32-bit bus clocked at roughly 100 MHz, as a separate domain.[237]
Removing the processor from a design entirely is sometimes the simplification: Greg Davill’s camera project replaced a dual-core RISC-V system-on-chip with pure Verilog that takes the camera stream and drives the LCD directly, leaving no CPU in the data path at all.[473] On mixed-signal chips, getting a very high sample-rate signal off the die is impractical, so digital reduction is done on-die: a ring oscillator producing one bit at one gigasample per second feeds a sinc or decimation filter written in Verilog that filters and downsamples, yielding for example eight bits at 32 megasamples per second at a rate the pads and bond wires can carry.[579]
Post-tapeout fixes
Fixing a defect in an already-taped-out chip is triaged on three axes: the engineering effort to implement, the desirability of the fix, and the risk that the change introduces new problems; the dominant cost question is whether the fix can be made as a surgical change to only the metal and via layers or requires a full re-spin.[687] A metal-layer fix works by rewiring existing logic gates and occasionally recruiting a spare gate from elsewhere in the design, so feasibility depends on how the logic was synthesised and whether timing budget is available; a defect in timing-critical logic can therefore be unfixable by metal alone even when the logic error is trivial, as with a register decode mask one bit too narrow, while the same class of error in slow logic is straightforward to edit into the metal stack.[687]
Two disciplines exist for gate-level fixes. One edits the gates, adds a register known as a chicken bit to disable the new logic, and proves only that the design reverts to its previous behaviour when the bit is off, which de-risks the change without fully understanding it. The other requires every gate-level edit to have an exactly logically equivalent change made back in the Verilog source, which is more work because the equivalent source change is often indirect rather than the obvious one-bit correction.[687]