| Episodes | 69 |
| Mentions | 101 |
| Cited here | 23 |
| First — last | #2 — #703 |
| Top guests | Dave Vandenbout, Mark Garrison, Dmitry Nedospasov |
| Related | verilog · fpga · hardware description language · microcontroller · asic |
VHDL is a hardware description language used to describe digital logic at the level of individual registers and logic structures, which is the source of the fine control that makes programmable logic worth using.[150] It is strongly typed and explicit, requiring a signal to be stated in effectively three places with all of them matching, and the tool reports at length when they do not.[469] That redundancy is the direct cause of the language’s verbosity and also removes an entire class of defect before simulation, since a mistyped identifier stops the tool rather than silently producing an additional object.[449][469] The VHDL and Verilog abstraction has held as a universal standard across decades of process and vendor change: RTL written without vendor-specific IP blocks can be pushed through different vendors’ FPGA flows and, with care, through an ASIC flow without modification.[650]
Verbosity and strictness
VHDL requires substantially more syntax and boilerplate than Verilog for the same design. In textbooks that print equivalent implementations side by side, the Verilog page is around ninety per cent white space while the VHDL page fills entirely.[303] The additional capability VHDL offers in some respects is paid for in declaration duplication, the same information restated in several places, and that duplication is the specific reason engineers who want C-like syntax use Verilog instead.[325]
The strictness has a compensating effect. VHDL will not accept a name that has not been declared and matched everywhere it appears, so a typo in a signal identifier halts the tool at that point rather than propagating into synthesis.[449] The result is a language that is slow to write and correspondingly hard to write wrongly.
Verbosity is not the same as low expressiveness. With the right macros and abstractions in place, an entire microcontroller can be described in a couple of hundred lines of VHDL that another engineer can read through and recognise as a processor, which matters because hardware description source is read far more often than it is written.[181]
The delta cycle
The delta cycle is a VHDL feature governing the state analysis of how concurrent processes interact within a simulation time step; Verilog implements the same idea differently.[237] Understanding it is the dividing line in a designer’s competence, since the error rate in written code drops sharply once the model is internalised.[237]
Verification
VHDL was built to support verification to a degree Verilog’s syntax does not allow, extending to theoretical proofs that a piece of hardware will function as specified.[303] The practical consequence is a mixed-language division of labour in which the design itself is written in Verilog and the test benches are written in VHDL.[303] The two languages coexist inside a single project with a designer using both at once, though a VHDL test bench carries over to a different target’s tool set only partially, so verification effort does not fully transfer when a design moves from FPGA to gate array.[147]
The language also supports a purely software-side career in hardware: some practitioners work only in the simulated domain, writing test benches and algorithms, and never take a design to physical hardware.[83]
Where VHDL is used
VHDL usage follows a geographic and sector split rather than a technical one: it predominates east of the Mississippi and across Europe, while Verilog predominates on the United States west coast and in Asia, and military work is largely VHDL.[181] VHDL was the default language for FPGA work through roughly the mid-2000s, and the balance has since moved, with chip industry work now predominantly Verilog and VHDL retaining a substantial minority of it rather than disappearing.[449] In the first Tiny Tapeout run, roughly thirty to forty per cent of submitted designs were written in a hardware description language, and the submission flow had to be split into separate automated build paths for Verilog, Amaranth and VHDL, since a shared entry point could not cover all three.[616]
Language choice among users of a development board is set by the language of the supplied example code rather than by the users’ own evaluation: a vendor providing all of its examples in VHDL sees its customers converge on VHDL.[181] At the opposite end of the scale, very low gate-count programmable logic parts are configured through a graphical design entry tool in which lookup tables and flip-flops are dragged, dropped and wired up, because at that gate count the effort of a hardware description language buys nothing.[65]
A large offshore supply of VHDL coding labour exists, sustained by graduate volume, competing on hourly rate and turnaround; the countervailing cost is quality, since cheap logic that has to be limped along and supported afterwards can outweigh the saving on hours.[70] Programmable logic distributors also staff field application engineers with FPGA expertise who will write VHDL for a customer to get a design running, which is how companies without in-house FPGA skill obtain it.[116]
Learning and moving between languages
Becoming able to program in VHDL is a formal-learning task measured in weeks of concentrated effort, unlike the incremental daily accumulation of engineering knowledge from reading and browsing.[256] Free vendor toolchains from Xilinx, Altera, Lattice and Actel are sufficient to learn on and ship extensive tutorials with the software; for experience that carries commercial value the recommendation is to learn on one of the two large vendors’ toolchains rather than a minor one.[103]
The gap to Verilog is syntactic rather than conceptual, and an engineer fluent in Verilog can write working VHDL with reference material to hand.[303] Moving in the other direction is equally practical on a deadline: an engineer trained in Verilog was moved onto a VHDL product and shipped it within about three months, learning by doing, and the VHDL content of successive digital test instrument cards was largely similar, covering streaming data to and from the host CPU, constructing test patterns, and checking for errors in responses.[138]
Migration away from VHDL is driven by tool and library availability. Open-source FPGA toolchains support Verilog more thoroughly, and the stock of existing example code and reusable cores is larger in Verilog, so choosing VHDL narrows the available tools and reference designs; VHDL cores do exist but in smaller number, and engineers who began in VHDL commonly switch when they start working with United States companies or on open-source projects.[467]
Generated VHDL
The register level becomes a liability for arithmetic-heavy work such as DSP, where hand-coding every function at register level each time is avoided in favour of a generator that emits the VHDL.[150] A common DSP path into programmable logic never has the engineer writing the hardware description at all: the algorithm is built as a block model in Simulink, the model is converted to VHDL, and the VHDL is pushed into the FPGA, with Simulink sitting at a much higher abstraction level than C so that the effective design language is the block diagram.[150] FPGA blocksets for Simulink, sold from around 2004 by Synplify and by Xilinx, let a designer assemble a math model graphically and emit VHDL or Verilog from it; the generated code makes the flow usable by an engineer who does not know the language well, but it is not maintainable source, so the model rather than the VHDL becomes the artefact that must be kept.[264] Migen serves a similar role from a different direction, a Python toolbox for building complex digital hardware that functions as a Python-to-VHDL compiler, generating the hardware description from a higher-level program rather than replacing the downstream flow.[428]
Design practice
When a VHDL design does not fit the target device, the two options are a larger FPGA or optimisation of the description itself; a logic analyser design that initially fitted only two channels was optimised rather than moved to a bigger part, over roughly four months of work before it fitted.[237]
VHDL frequently occupies a defined slot within a partitioned system rather than the whole device. One commercial FPGA module platform reserves fixed vendor IP for the bus interface and DRAM, leaves a window for high-level graphical code, and leaves a second window for user VHDL that interfaces to the analogue circuit; the user’s VHDL is the low-level layer that configures the clocking chip, monitors temperature and captures ADC data, and the vendor documents the timing and mechanical constraints for it in a module developer kit.[138] Vendor instrumentation is delivered the same way: a plugin instantiated in the user’s VHDL taps the FPGA die’s 10 Gbit transceiver and streams the raw recovered data to a PC application that computes average and peak bit error rate over days of running; every parameter is tweakable, so the same setup can be tuned until almost any link passes, and results are only meaningful with the tweaks and the temperature stated.[148]
An open soft core distributed as VHDL source, such as the ZPUino, serves as an alternative to a vendor’s own processor core, whose tooling is closed and not available to modify without a full licence.[232] Because the source is open, custom peripherals slide into the core easily: a simple RGB LED controller added as a peripheral generates the PWM waveforms continuously in logic, so the processor only pokes it occasionally instead of driving the waveforms itself.[232] Legacy processor cores can likewise be reimplemented from the ground up in VHDL and shipped in silicon without royalty exposure where the relevant patents have lapsed or the core was released — the 6502’s instruction-set and mnemonic patents have long expired and Intel placed the 8051 in the public domain — whereas embedding an ARM core costs a per-unit royalty or a fixed fee negotiated up front for very large volumes.[169]