| Episodes | 155 |
| Mentions | 308 |
| Cited here | 77 |
| First — last | #1 — #720 |
| Top guests | Sam Zeloof, Andrew Seddon, Jeff Keyzer |
| Related | wafer · silicon · economies of scale · moores law |
A semiconductor fabrication plant (fab) is the factory in which integrated circuits are built on wafers, and it is one of the most capital-intensive industrial facilities in existence: a commodity-chip fab costs on the order of $5 billion to build, a disparity against a twenty-cent part that forces semiconductor manufacturing into extreme volume.[4] Rising fab cost has progressively shrunk the number of companies able to own one, driving industry consolidation and the growth of dedicated foundries such as TSMC, and making the fabless model the default structure for new chip companies.[54][310] Because each process step takes a long time regardless of how many die are on the wafer, fab economics push toward maximising chips per wafer and keeping the process equipment running at 90 to 95 percent utilisation.[63][32]
Capital cost and economics
Quoted construction costs have climbed steadily with each generation: around 2012, converting an existing 300 mm line to 450 mm wafers was quoted at about 5 billion for a complete new fab, and TSMC’s first 450 mm plant was quoted at eight to ten billion dollars.[63][100] A new leading-edge fab has since been put at ten to fifteen billion dollars minimum, and may not turn a profit for roughly five years after it is built.[310][52] Wafer-size conversions are done in stages, routing some wafer types to converted tools and others to the old tools, because fabs avoid downtime wherever possible.[63]
Reaching a new process node first confers pricing power: the leader can charge what it likes for parts nobody else can make until competitors catch up, and that window is how a $5–10 billion fab investment is recovered.[64] A full process-node lead — for example a 20 nm line while others were a node behind — is bought with capital rather than won on design.[94]
Fab economics work as a reverse annuity: a multi-billion-dollar loan buys the building and machinery, and every wafer sold thereafter pays down that machinery, which is why prices fall as a process moves to the trailing edge.[672] Because a decent fab represents a five-to-ten-billion-dollar investment, the operator runs it for twenty or thirty years; once the plant is paid off many times over, the chips coming out of it get progressively cheaper.[176] A fully depreciated older line, such as a 500 nm fab, can remain commercially interesting because the capital is written off and process variation at that geometry is not a significant constraint.[54] A trailing-edge line such as 180 nm — roughly a dozen generations behind the leading edge — is kept running because the equipment is already paid for, and the resulting excess capacity can be sold cheaply to new kinds of customer even though its marginal cost is not zero.[616]
Fab ownership itself is a low-margin business, absorbable only by companies large enough to treat a couple of billion dollars as incidental.[118] Burr-Brown ran its own four-inch wafer fab in Tucson, which was shut down after acquisition because a four-inch line was becoming obsolete and the company could not fund a large modern fab; four-inch production is now economical only for very high-value parts, and for an ordinary chip selling between fifty cents and three dollars even six-inch wafers are not viable.[348][169] For laboratory research on a new material, one-centimetre wafers are adequate, but a real manufacturing process needs four- or six-inch wafers, with cost per die rather than yield alone as the driver.[71]
Foundries and the fabless model
A foundry is a fab that sells its process capability to outside customers: TSMC is the canonical example, Samsung maintains foundry capability alongside its own products, GlobalFoundries was spun out of AMD, and SkyWater runs open-source process offerings.[685] With a new leading-edge fab costing ten to fifteen billion dollars, new entrants cannot build one, so access to an existing fab is the only route to silicon and the fabless model becomes the default industry structure; a startup might face $2 billion up front to own a fab, and no startup can raise the roughly one billion dollars needed to buy an existing one.[310][129][44] The analogy is a new board maker using an assembly house before buying its own SMT line.[44] The compensating benefit is that a small startup with a good analog layout engineer gets access to the same fabs and design tools as a company with its own ten-billion-dollar fab.[310]
Owning a fab imposes a fixed capacity ceiling — for example 20,000 wafer starts a week — which must be rationed among customers, whereas farming out to a foundry removes that ceiling.[44] Divestiture of fabs has taken striking forms: GlobalFoundries exists because AMD split its fabs out of the design company, and IBM exited manufacturing by paying GlobalFoundries to take its fabs, an inversion of a normal sale that shows a fab can be a net liability.[351][249] Traditional analog makers likewise divested their own fabs once chartering wafers from a large foundry became cheaper than operating a small, old line.[169]
Being fabless does not level the field entirely: the largest FPGA vendors keep process-technology staff working directly with TSMC and UMC on custom processes, and may hold exclusive access to a new process for its first year.[103] Conversely, when two competitors use the same foundry and the same node, the process is no longer a differentiator and the only remaining variable is design and verification speed.[136] A leading-edge foundry serves FPGAs, custom ASICs and large SoCs rather than analog parts, and a large customer will put a design out to bid across TSMC, Samsung and Intel and choose on price and availability.[576]
Analog vendors have split on strategy: Texas Instruments continued to run its own fabs as a competitive strength, Linear Technology likewise kept its own fabs while Analog Devices mixed in-house fabs with the TSMC foundry model.[270][310] The case against divesting is that the process is the differentiation for an analog company, and that giving up process technology also gives up tribal knowledge and the incremental innovations that come from being on the shop floor — a cost that does not appear on the financial case for going fabless.[278][504] For FPGA vendors, the defensible know-how is similarly in manufacturing at scale with good quality, reliability and yield, plus test techniques, held as trade secrets rather than patents.[525]
Process development is a foundry’s core intellectual property, so process design kits are traditionally released only under NDA even though designers need them to target the process at all.[616] Google’s open-source PDK programme paired an openly published kit with free wafer fabrication at 130 nm, on the condition that the design itself be open source.[500]
Process technology
The leading-edge logic process moved to FinFET and other three-dimensional transistor structures to preserve its performance advantage; TSMC’s 16 nm FinFET process, the qualified successor to 22 nm, ran at a core voltage of 0.55 V.[94][246] Below the FinFET nodes, printed dimensions are smaller than the deep-UV wavelength can resolve, so a single layer is decomposed into several coarser patterns exposed on top of one another — multiple patterning — which buys the fine resolution but removes layout freedom: devices can no longer be placed in arbitrary orientations, and everything on a patterned layer must run in the same direction, one of many rules that make modern design-rule-check decks enormous.[553] Only two or three companies in the world can run 5 nm and 3 nm class CMOS processes, and the rising cost of each node is the counterpart to the flattening of Moore’s law.[553] EUV patterning machines cost over a hundred million dollars each and are what a 3 nm process requires, so a plant budgeted at $1.2 billion cannot be a leading-edge line.[546]
Feature size is not uniform across a die: the gate is the tightest dimension, so selective patterning routes gates through the newest and most accurate exposure equipment while larger features are printed on older tools.[666] At the leading edge of around 7 nm, transmission electron microscope cross-sections of transistors are on the order of 50 to 70 atoms wide.[390]
Process history is not monotonic. Metal-gate MOSFET processes were abandoned in the 1970s and returned decades later when polysilicon and silicides stopped working at very small feature sizes, and many techniques dropped in the 1960s and 1970s were abandoned for throughput reasons rather than because they did not work — making older process literature useful to anyone recreating a process at low volume.[52] Older fabs ran much of their etch and ash equipment essentially open to the air, while modern equivalents are high-vacuum chambers, and that vacuum is what makes the fine geometries achievable.[134]
There are physical reasons not to move analog parts to small nodes: leakage at 16 nm demands elaborate compensation, and a trench power FET needs geometries orders of magnitude larger.[559] A further practical block is tooling rather than physics, since the analog design package for those processes is not made available.[559] A switching power supply will be built on a 90 nm or 45 nm process even at its most advanced, so leading-edge fab investment does not address shortages of that class of part; conversely, useful products can still be built on an old node such as 180 nm when die size and power are not constraints.[582][111] Improving fab technology let more current be carried on-die, which is why switching regulators migrated from controllers with external FETs to converters with integrated FETs.[273]
Process variants serve particular markets. High-speed and RF parts are typically built in silicon-germanium BiCMOS, in which SiGe bipolar devices give higher breakdown voltage and power handling while ordinary, non-advanced CMOS sits on the same wafer as a helper.[553] CMOS image sensors are made on a comparatively standard semiconductor process, allowing control logic and ADCs on the same die, whereas CCD sensors need a specialised process.[325] Silicon carbide cannot be pulled from a melt the way silicon or sapphire can, because it does not melt, so SiC boules must be grown by a different method entirely.[71] IGZO (indium gallium zinc oxide) processes have been used for MEMS-adjacent research run in low-grade R&D fabs rather than production lines.[371]
Tape-out and yield economics
Die size drives yield sharply: a die a centimetre on a side must yield well or the process is out of control, because defect density tolerable on a small die is fatal on a large one.[103] Mask-set cost at the most current process technology has exceeded ten million dollars, and the rise of that cost with each node shrink steadily narrows the range of applications where an ASIC beats an FPGA.[103] A multi-project shuttle run gives low-volume silicon for a couple of hundred thousand dollars, with moving the same 20 nm design into volume production costing about three million dollars more; a small shuttle slot runs around ten thousand dollars, which is why commercial tape-outs justify exhaustive simulation.[254][390] Cheap-respin services commoditise the process by fixing the transistor array and customising only the metallisation layers over the top, making a few-hundred-dollar prototype possible, and small companies have chosen fabs running older processes specifically because that was the tape-out they could afford.[201][338] Geometry errors on a mask are unforgiving: the first run of a 400 V, one-ohm power MOSFET came back at two ohms because one drawn dimension between openings was 10 microns instead of 15, forcing the whole design to be discarded.[719] For anyone fabricating semiconductors by hand, surface states are the dominant obstacle; the first transistor only worked once the contact tip was immersed in an electrolyte.[328]
Facilities and siting
A fab building is roughly ten storeys tall, of which the fab floor itself may be three storeys of open internal space, with hollow service floors below carrying pumps, piping, water, chemicals and power for the tools above; roof trusses span the full width of the building so the process floor is free of pillars, and large fabs are built as stacked structures with one fab floor on top of another to multiply capacity on a single site.[666][353] One plant measured about nine football fields across, made up of nine bays side by side.[210] The hard part of building a fab is the facility rather than the shell — the sub-basements, piping and utility logistics needed to feed the tools, including very large volumes of water.[210]
Water is a first-order siting constraint and a real production risk: Taiwan had to reduce chip output during a water shortage.[598] Ground stability matters because lithography alignment cannot tolerate vibration, so porous limestone bedrock that absorbs vibration and low seismic activity are siting advantages.[579] Analog Devices built a fab in Ireland on the strength of tax incentives plus the ease of flying wafers in and finished chips out, and the resulting cluster attracted further semiconductor investment and graduates to the region.[579] Fabs are heavily chemical-dependent, so a supporting ecosystem of chemical suppliers and service companies grows up around an established site.[176]
US fab work is geographically concentrated — Oregon, Boise, Arizona, Richardson in Texas, Austin, and the Albany and East Fishkill area of New York — and process work on the floor cannot be done remotely, so the industry constrains where its engineers can live.[530] Siting a fab away from an existing cluster creates a staffing problem, since the nearest comparable fab may be many hours’ drive away and experienced process staff have to be recruited or developed from scratch.[576]
Operations
Modern chip fabs are largely fully automated, with wafers moving through the line and tested chips emerging with little manual handling.[219] A wafer’s route through the fab is a supply chain in miniature — photolithography exposes the wafer, it is rinsed, then it moves to dry etch or ash — and a fault at any station backs up everything behind it.[502] Because a fab line is designed for full utilisation, a single tool going down costs both the lost capacity and a growing queue of work in progress behind it.[120] Etch chambers foul as wafers are processed, so the quartz kits inside them must periodically be swapped out, after which the chamber is pumped down, tested and verified before returning to production.[120] An unplanned power loss in a plasma etch chamber drops the material suspended above the wafer straight onto it, scrapping large numbers of wafers in progress.[536] Cleanroom garments are managed as a consumable-like resource: after wear they are laundered to remove particulates and re-wrapped.[166]
A microcontroller vendor’s fab can hold several generations of technology in production at once — EPROM, EEPROM and Flash processes all continue to run, supporting thousands of part variants — and switching between them is a scheduling matter rather than a fab conversion, since different mask sets can be started on consecutive days or on the same day because the fab holds enough equipment to run the processes in parallel.[632] From the customer’s side, buying semiconductor capacity means being given a slot on existing equipment, unlike commissioning a specialised supplier that may build production lines and even buildings to support one customer’s product.[365]
Supply chain, lead times and shortages
The quoted internal cycle for a chip order is roughly thirty days to make the silicon, then dicing, packaging and test, and then a wait to be slotted into the fab’s schedule; no customer gets a dedicated line.[197] Complex parts such as large FPGAs are often made to order: the distributor passes the order to the fab and the process takes about six months, during which the rest of the bill of materials accumulates at the assembler as tied-up cash.[699] A dominant customer can demand the entire output of a production line for a new product, pushing every other customer down the queue, which is a recurring cause of apparent shortages.[366]
Fabs are slow to restart. The post-2008 shortage came from the whole chain stopping at once — orders cancelled, backlogs sold off, workers laid off — and a fab cannot be restarted quickly once shut down; lead times of 30 to 40 weeks were seen after fab shutdowns, which is why high-volume designs carry second and third sources for critical parts.[366][5] Restarting mothballed fabs is not a fast route to capacity either, because the capital equipment is sold off when a fab closes and what remains is essentially an empty building.[541] When a foundry is congested, every customer of that foundry sees the same lead times, so which fab a vendor uses becomes a supply consideration when choosing between otherwise similar parts.[384] Consolidating many products onto shared foundry capacity concentrates risk: when one fab goes down, a large fraction of a designer’s parts become unavailable at once, an effect visible during the COVID-era shortage.[628] Unlike passives, silicon parts are largely not interchangeable during a shortage, so a shortage of one switching regulator cannot be designed around cheaply.[541]
Fabs periodically retire process nodes, and the customer’s option is a last-time buy: the fab announces a final run and the buyer orders enough parts — potentially a million — to cover the remaining product life.[646] When a vendor changes a part’s fab or process node, it issues a product change notification that propagates through distributors, so behaviour and specifications can shift on an otherwise unchanged part number; the same ordered part can come from any of several manufacturing plants worldwide, because wafer fabrication and packaging happen in different places.[727][157] The industry is split by task and geography: the fab produces the wafer, which is shipped to another country for packaging and elsewhere again for die bonding and test, and no existing factory does the whole sequence on one site.[720] In wafer-level chip-scale packaging the finished wafer is not diced at the fab: it goes to a packaging fab where polymer insulator, vias and a couple of copper redistribution layers route the die pads out to solder balls placed directly on the wafer, and only then is it cut into chips; incoming wafers are around 500 microns thick or more and are usually ground down so finished chips end up a few hundred microns thick.[469]
Policy and national programmes
Fab capacity moves between countries only over decades; obsolete plants are typically neither upgraded nor relocated but left to run down and become brownfield sites.[111] The United States committed about 15 billion, so the programme could fund only a small number of plants; once funding was in the pipeline, the announced fabs were expected to take two to three years or more before running, raising the possibility of a glut at the far end of a shortage, and roughly forty billion dollars had been distributed as the programme began paying out.[532][598][666] Microchip examined the CHIPS Act terms, judged that “it was golden handcuffs”, and declined the funding; several other announced fab projects were scaled back for the same reason.[694] Foreign fab construction in the United States is driven substantially by politics, tax breaks and onshoring policy rather than by manufacturing logic alone.[494] The difficulty of spinning up a fab is illustrated by a state-backed startup in China that consumed billions of dollars over roughly five years and produced nothing, having failed to secure either the staff or the continued funding needed.[536]
Fab capacity is also limited by the machine builders: the tools are hugely complex, and getting the machines that make chips is harder than getting chips.[530] Fab construction has a natural time limit that capital cannot compress — the industry’s answer to demands for more capacity during the shortage was that new plants take about six years to build.[699]
Small-scale and home fabrication
The barrier to home or small-scale chip fabrication is the number and complexity of the chemical process steps rather than the patterning itself; the same step count is why production fab houses cost hundreds of millions of dollars at minimum.[20] Production fab chemistry is chosen for throughput, using the strongest practical acid concentration to push hundreds of thousands of wafers through, whereas a home process can substitute far milder chemistry — such as a rust and stain remover — and simply wait twenty minutes for an oxide etch.[52]
Sam Zeloof assembled a garage semiconductor process from eBay and Amazon — wafers, chemicals, general lab supplies and a furnace — after establishing through conversations with industry practitioners which chemicals and safety measures were needed; his recommended single-volume introduction is Peter Van Zant’s Microchip Fabrication, about 400 pages and free of heavy mathematics.[390] A home fabricator writes their own design rules: a .tech file for Magic VLSI encoding minimum and maximum spacings, layer thicknesses and MOSFET characteristics lets the layout tool enforce what the garage process can actually resolve, and the work draws on several disciplines in sequence — device physics first, then the chemistry of the process steps, then optics once a lithography setup is being built.[390] Owning the process changes the design economics: a simple three-transistor circuit can be checked by inspection and a mistaken mask simply remade, whereas a commercial tape-out must be simulated exhaustively because the run cannot be repeated cheaply.[390]
Used semiconductor process equipment is cheap at older geometries — a used sputtering machine runs roughly 1,000, and equipping a one-micron line is affordable because that is 1980s technology.[245] Direct-write rastering substitutes for mask-based exposure in a garage process, which is precisely why such a setup cannot reach volume: a mask prints many chips in one exposure and rastering does not.[597] At the industry scale, semiconductor manufacturing is unusual in that the equipment is catalogue-purchasable from suppliers such as Applied Materials or Tokyo Electron; Atomic Semi was set up to build small, fast semiconductor fabs and to own the whole process from raw silicon upward, in reaction to the difficulty of buying the equipment and materials the industry depends on.[500][621]