SPICE, an acronym for Simulation Program with Integrated Circuit Emphasis, is a family of numerical circuit simulators originally developed for silicon integrated-circuit design rather than board-level or macro-scale circuit design.[195] A SPICE simulation is normally defined by a text netlist and simulation directives, which may be generated by a schematic-capture program or supplied directly to a command-line solver.[148][195] The tools are used to evaluate circuit behavior before physical implementation, with their principal practical advantage being the ability to change components or circuit parameters without constructing or modifying hardware.[7][210]
Origins and terminology
SPICE was created for transistor-level integrated-circuit analysis, and its later use for discrete circuits and printed circuit boards extends the simulator beyond its original design scope.[195] SPICE-family programs have existed since the 1970s, and their lineage remains visible in later program names, including NGspice’s descent from Nutmeg-era work.[505]
The name SPICE can refer both to the original simulator lineage and, more generally, to simulators that solve a circuit through a global Jacobian matrix.[196] The underlying SPICE engine is open source, although graphical or vendor-supplied programs built around such an engine are not necessarily open source themselves.[168]
LTspice was written by Mike Engelhardt, who had been developing physical simulators since 1975 and had already written two circuit simulators before it.[196] Engelhardt developed LTspice after concluding that established numerical methods, together with methods he devised himself, could produce a faster and more robust SPICE implementation.[196] The LTspice engine made available to Linear Technology customers was also used internally by the company’s designers to develop its integrated circuits.[501]
Architecture and numerical methods
Netlists and solver cores
A graphical SPICE program functions primarily as a schematic-capture front end that translates a drawing into a text netlist for the solver.[148] The solver itself is fundamentally a command-line program that reads the netlist and simulation directives from a text file and executes the requested analysis.[195]
Competing SPICE products are therefore largely wrappers around similar solver technology, with much of their product-level development concentrated in schematic entry, model management, waveform display, and other parts of the user interface.[195] Solver algorithms have nevertheless improved over time, particularly in convergence behavior, although such changes are less visible to users than changes to the graphical interface.[195]
For an electronic-design-automation vendor, generating a valid netlist and obtaining appropriate device models from a captured schematic can be more difficult than supplying the numerical solver itself.[163] A tool may consequently contain a capable SPICE backend while still requiring the user to provide a netlist manually.[163] Because the solver is open, text-based, and long established, attaching it to a CAD package is comparatively inexpensive; the larger engineering effort lies in constructing a reliable interface around it.[163]
Nonlinear and differential-equation solution
SPICE solves nonlinear circuits by successive linear approximation: it repeatedly formulates the circuit as a system of simultaneous equations and solves the corresponding matrices.[196] A simulator using a global Jacobian can be regarded technically as a SPICE simulator, distinguishing that formulation from tools that solve circuits by other methods.[196] For RLC circuits, this numerical process corresponds to the kind of analysis otherwise taught through Laplace transforms, although the simulator does not need to evaluate such transforms directly.[196][276]
A SPICE simulation has separate accuracy controls for nonlinear device behavior and for the ordinary differential equations introduced by capacitors and inductors.[196] The TRTOL parameter controls the accuracy with which those differential equations are integrated, independently of the precision used to solve the nonlinear current-voltage relationships.[196] Industry SPICE programs conventionally set TRTOL to seven, whereas LTspice sets it to one, an order of magnitude tighter, so that integration artifacts are less likely to be mistaken for circuit behavior.[196]
From 2008, LTspice became self-authoring: after parsing a netlist into internal data structures, it generates, assembles, and links an assembly-language routine specific to that circuit and then calls that routine as a function.[196] Generating circuit-specific machine code removes layers of pointer indirection associated with dynamic memory allocation and makes the simulator approximately three times faster, because moving operands into the floating-point unit can cost more than the arithmetic operation itself.[196]
Writing simulation software is principally an exercise in numerical mathematics, while device physics becomes central when constructing the models themselves.[512] Examples include models that describe how semiconductor behavior changes with temperature for thermal or Monte Carlo analysis.[512]
Role in circuit design
Integrated-circuit design
Analog integrated-circuit design begins at the schematic level with foundry-supplied SPICE transistor models.[706] The designer constructs test benches around those models and simulates the schematic before any layout exists.[706]
The design variables available during transistor-level simulation have narrowed with process generation.[706] Bulk CMOS permits transistor width and length to be swept continuously, whereas FinFET design reduces the choice largely to a discrete number of fins or fingers.[706]
After layout, parasitic extraction converts the physical drawing into a much larger netlist.[706] Each wire is represented as a chain of small series resistors with capacitances to ground and to neighboring wires, allowing coupling between nets to be modeled explicitly.[706]
The final verification test benches used for the schematic are then rerun against the parasitically extracted netlist.[706] Because the extracted circuit is substantially larger than the original schematic, a complete verification run can take on the order of two weeks.[706] When an extracted simulation fails, the netlist can be bisected, or individual nodes can be extracted separately, to identify the parasitic element responsible for the failure.[706]
As operating frequencies rise and parasitics become more significant, schematic design and layout are more commonly performed by the same person rather than split across a designer and a dedicated layout drafter.[706]
Board-level design
At the board level, SPICE allows component values and part types to be changed immediately without maintaining a physical parts inventory or desoldering components.[7] Simulation is especially useful when it is faster than breadboarding, when parts are unavailable, or when only a circuit concept needs to be tested.[210]
A practical workflow is to take a known-good topology from a reference source, simulate it to confirm the expected behavior, and then commit it to hardware.[244] Simulating a circuit before breadboarding also creates a reference against which the physical construction can be checked, allowing discrepancies to identify a specific difference between model and hardware rather than an unknown fault.[210]
Simulation is most effective when the designer already understands the behavior of the underlying components.[210] Without that foundation, changing simulated values can degenerate into trial and error without explaining why a modification improved the circuit.[210] For Tom Lee, an experienced analog designer, the threshold for using simulation is set by the possibility that an expert may correct a circuit by inspection in less time than a less experienced engineer requires to enter the netlist.[459]
A passing simulation does not qualify a design for production, because the model does not represent every physical, manufacturing, and assembly effect present in the finished product.[210] Assembly and wiring defects such as shorts or missing pull-down resistors likewise require hands-on examination of hardware rather than schematic-level simulation.[454]
Filter and mixed-signal design
Active-filter design involves a direct trade between stage count and settling behavior: fewer stages produce a longer step response, while more stages can settle more quickly.[392] Filter order is therefore selected against the required settling performance.[392]
Vendor design wizards may export generated circuits as SPICE netlists so that the result can be independently verified or extended with passive stages that the wizard cannot generate.[392] In mixed-signal systems, instruction-set simulation of a microcontroller can be paired with SPICE analog simulation so that the timing of the digital edges driving the analog circuitry is correct at the individual-instruction level, regardless of the higher-level software stack.[471]
Signal integrity and electromagnetic compatibility
Signal-integrity work uses rules of thumb, closed-form spreadsheet approximations, and numerical simulation according to the accuracy required by the question.[252] Rules and approximations provide rapid intuition, while numerical simulation is reserved for cases that the simpler methods cannot answer.[252]
Multiple reflections on a branched interconnect cannot be tracked reliably by mental calculation or a simple formula, making SPICE the practical means of determining the resulting noise margin.[252] Crosstalk as a function of conductor cross-section lies outside circuit simulation and requires a two-dimensional field solver rather than SPICE.[252]
The customary 100 nF decoupling capacitor suited systems with clocks in the tens of megahertz, but at approximately 100 MHz such a component can be above its self-resonant frequency and behave as an inductor rather than contributing useful capacitance to the power-distribution network.[169] A rigorous electromagnetic-compatibility investigation can therefore remove the switching regulator, power the board from a clean analog supply, and measure power-distribution impedance against frequency with a network analyzer and bias tee.[169]
Models and limitations
Device and component models
When a schematic is imported into a simulator, resistors and capacitors can generally be assigned generic models automatically, but every active device must already exist in the simulator’s model library or be assigned manually.[148] Vendor models are frequently tuned to the vendor’s own simulator, and making third-party subcircuit models operate in another package is a recurring source of setup difficulty.[188]
Manufacturer op-amp macromodels may violate Kirchhoff’s current law by allowing current to appear or disappear inside the model, making supply-current and power results unreliable.[476] Impossible outputs such as gigavolts at an op-amp node generally indicate a limitation of a Boyle-type macromodel rather than a fault in the solver, so the appropriate correction is to change the device model rather than merely alter simulation settings.[196]
Internally compensated op-amps are optimized by their manufacturer for stability, whereas an uncompensated device places the entire stability-verification burden on the circuit designer.[141] SPICE models are also not constrained by thermodynamic consistency and can produce noise or energy results that no physical device could produce.[476]
Some component behavior is difficult to express in a straightforward SPICE model.[5] A solar cell, for example, depends jointly on illumination and junction capacitance rather than on a simple diode-like current-voltage curve, making accurate simulation difficult.[5] Transformer specification is another weak point, particularly because leakage inductance and related parameters are handled inconsistently across simulators.[17]
SPICE interprets the suffix M as milli rather than mega, so a resistor entered as 10M is treated as 10 milliohms; megohms must instead be entered with an explicit mega designation such as Meg.[76] Ceramic capacitor values are specified at zero volts DC bias, so a component operating at a real working voltage can deliver substantially less capacitance than its marked value, a reduction not represented by a simulation using only the nominal value.[169]
Physical effects outside schematic models
A common-mode rejection failure can survive both simulation and ordinary component measurement when the relevant physical coupling is absent from the schematic model.[169] In one such case, the SPICE model predicted correct operation and the inductors met their measured value, Q-factor, drift, and tolerance requirements, but the assembled board still failed.[169]
The cause was the internal winding orientation of air-core inductors, which varies by manufacturer.[169] Horizontally oriented coils on adjacent components can couple strongly enough to form an unintended common-mode transformer, while vertically oriented coils do not produce the same coupling.[169] This physical orientation is not represented in an ordinary schematic-level SPICE model.[169]
More generally, treating SPICE as able to answer every circuit question is a misuse of the tool.[17] Simulation occupies a defined place in the design flow, and effects omitted from the models remain the responsibility of physical measurement, layout analysis, field solution, or bench debugging.[17][169][252]
Software ecosystem
Large semiconductor vendors have supplied SPICE front ends associated with their component catalogs: Texas Instruments offers TINA, Analog Devices had a tool developed jointly with National Instruments, and Linear Technology offered LTspice.[130] Such products provide model access and schematic integration around a solver, while the underlying SPICE engine and the vendor package remain distinct pieces of software.[130][168]
KiCad incorporates a SPICE engine at no additional cost to the user, although the integration inherits the practical difficulties of combining a schematic editor and model interface with an existing solver.[380] Passive-component manufacturers also increasingly publish SPICE models and exportable simulation data alongside part-selection tools, moving more model-development responsibility upstream to the component vendor.[596]
The open-source integrated-circuit design flow uses several distinct SPICE-family simulators rather than a single integrated suite, including LTspice, Zeiss, XYCE, NGspice, and MicroCap.[501] Parasitic extraction in that flow is handled separately by tools such as FastCap and FastHenry.[501]
Simulator development can cost more than licensing revenue can recover, particularly for the highest-performing tools in a specialized engineering field.[196] Companies that require such capability may therefore build simulators internally as part of their design infrastructure rather than develop them as commercial software products.[196]