| Episodes | 200 |
| Mentions | 313 |
| Cited here | 84 |
| First — last | #3 — #722 |
| Top guests | Robert Feranec, Mike Harrison, Sergiy Nesterenko |
| Related | schematic · altium · kicad · datasheet · design rule checking |
PCB layout is the stage of printed circuit board design in which components are physically placed and copper connections are routed to implement a schematic. The stated function of the board is to execute the schematic faithfully: an ideal board would have zero trace length and no parasitic resistance, inductance or capacitance, so every real board is an approximation of that ideal.[626] The layout is itself a circuit component, since the same schematic built by two designers can produce circuits that measure differently, which is why power integrity is treated as a design discipline rather than a layout detail.[476] Within the wider task of turning a circuit into a board, layout rather than schematic capture consumes the bulk of the effort, to the point that PCB design is characterised as ninety percent layout.[410]
Placement
The working rule among professional designers is that layout is ninety percent placement, so routing quality is largely decided before the first track is drawn.[412] The rule is long established enough to be treated as an adage, and it is the reason a board that looks unroutable in the rat’s nest phase is usually judged by its placement rather than its unrouted state.[682] Decisions taken at the very start of a layout constrain everything that follows, so early placement choices carry disproportionate weight compared with later routing choices.[8]
Traces that run the full width of a board are treated as a placement failure rather than a routing problem, because a long crossing trace obstructs every other net that must cross it; the correct response is to ask why the connected parts are not placed nearer each other.[410] Board dimensions can be allowed to emerge from the mechanical and electrical constraints during layout rather than being fixed beforehand, and deliberately leaving spare board area preserves room to shuffle parts or add features later.[436]
Choosing a passive package size for a given board is done by judgment from board area and part count rather than by calculation: a dense design is identified as an 0402 design by eye at the start, and no useful calculator exists because the variable space is too large and the outcome is only known at the end of the layout.[488] High-end PCB packages provide component and routing density heat maps that show where a board is becoming congested, a feature that has long existed in professional tools.[488]
Physical and package constraints
Large isolated thermal pads act as routing keepouts that destroy local layout density and force other nets to detour around them.[516] The exposed centre ground pad of a QFN package cannot be routed through, so it blocks board area that a designer may otherwise have counted on when estimating density.[488] Ball grid arrays at 0.25 to 0.4 millimetre pitch cannot be escaped using ordinary prototype fabrication capability, so the available fabrication class rather than the designer’s skill sets the upper bound on usable packages.[520]
Component height is a layout constraint set by the enclosure, since a tall capacitor placed without reference to the mechanical design will collide with plastics that are already fixed.[342] In-house PCB milling constrains layout further: a milled prototype must be redrawn around the mill’s minimum feature capability, and a design taken to a fabricator afterwards generally needs reworking because the choices made for the mill are not the choices made for production.[454] Home-etched boards have no plated through holes, so a double-sided layout made this way requires a wire fed through each via and soldered on both sides, and spreading the design out on one side is often the cheaper trade.[32] Two single-sided milled boards can be routed separately, flipped and laminated together to obtain a double-sided prototype in real copper.[236] Boards intended for hand assembly as kits are laid out with deliberately enlarged pads on the few surface-mount parts so they remain solderable by hand.[73]
Above roughly ten megahertz, or where sampling rates make trace parasitics significant, breadboard and flying-lead prototyping stops representing the circuit and a laid-out board becomes the only realistic prototype; many modern packages are not breadboardable at all without first laying out a breakout board.[110]
Stack-up and power distribution
Moving from two layers to four removes power distribution from the routing problem entirely, because supply nets go on internal planes, and multiple supply rails on a four-layer board remain manageable for the same reason.[221] Going straight to a four-layer stack-up with a solid ground plane is used as insurance against compliance failure, on the reasoning that the extra board cost is smaller than the cost of failing an emissions test.[424]
Signal integrity and electromagnetic compatibility
Radiated emissions failures seen in electromagnetic compatibility consulting are usually caused by bad layout, specifically a poor understanding of ground planes, since the governing quantity is the impedance of the radio-frequency ground return.[424] Keeping current loops tight, particularly high-current loops, is a primary emissions control, and the same tight loop reduces the receiving area of the board, so immunity improves as a by-product of the emissions work.[472] A physically small board gains electromagnetic compatibility margin for free, because every current loop it can form is bounded by its dimensions.[175]
The first step in laying out a mixed-signal board is to visualise where currents will flow and partition the board so that high-current, high-noise and high-frequency paths are kept out of sensitive analogue areas.[185] As clock rates rise, trace characteristic impedance, differential pair matching and trace length matching become real circuit elements that appear nowhere on the schematic, so they must be controlled during layout or not at all.[185] Physical proximity of conductors is irrelevant in a logic schematic but has a large effect in the built circuit, which is the transition digital engineers moving into board design have to make.[77]
A high-speed digital link can pass functional testing while a layout defect shows up only as a rare bit error, so bit error rate testing run continuously over hours is the measurement that exposes it.[668] Electromagnetic compatibility training treats board layout as one topic among cabling, grounding, shielding, decoupling and filtering, with digital layout and grounding and mixed-signal layout taught as distinct subjects, and layout and stack-up is substantial enough to occupy a full chapter comparing layer combinations in a reference text of nearly nine hundred pages.[165]
Modern surface-mount capacitors reach equivalent series inductances of roughly twenty-five to forty picohenries, less than the inductance of the traces connecting them, so a poor layout can negate the performance of a high-specification capacitor.[596] A monolithic class D amplifier needs little layout work beyond two second-order LC output filters, but an imbalance in the inductor and capacitor configuration, so that the impedances at each end do not match and fluxes do not cancel, produces a startup click or pop and shows up on radiated emission scans.[474] In a multi-phase buck converter the input and output ripple reduction obtained from paralleling phases depends on the quality of the layout.[566] Star earthing was learned in audio design as the direct consequence of layout on measurable output, since a wrong grounding layout in an audio amplifier produces audible hum.[481] Microcontroller immunity to a nearby electrical discharge has been qualified by striking an arc directly above the device on the assembled board and requiring that it not reset, an outcome that depends on the device chosen and then on layout and decoupling.[481] Integrating the two switching transistors of a buck converter into one package, with the source of one internally connected to the drain of the other, simplifies the layout and reduces losses between the devices.[340]
Field simulation and visualisation are used to build intuition rather than as routine design steps: once the intuition exists, a designer can inspect a layout and identify where a problem will occur without running the simulation.[681] An open-source electromagnetic simulation flow for a board antenna consists of exporting the layout geometry with its copper as an STL file into the field solver and defining a mesh deliberately dense in the region of the antenna.[695]
Power supplies and component substitution
Switch-mode power supplies are heavily layout dependent, so substituting a switching regulator forces a much larger requalification than substituting a linear regulator, which usually needs only local rearrangement to keep the decoupling capacitors close.[601] A switching converter feedback path routed as a large loop from the output back through the feedback network to the controller is a layout defect; the loop must be kept tight, and such errors are typical of a layout done at speed.[561] A forced switching-regulator substitution can cascade into new passive selection and a package change to QFN, BGA or wafer-level chip-scale, which in turn can force blind and buried vias and a fabrication class change for the whole board.[601] A single part substitution forced by supply shortage can propagate well beyond layout: a one-letter change in a part number can alter memory size, peripheral set and package, requiring a layout change, firmware rewrite and revision of the system diagram together.[587]
Semiconductor vendors publish reference layouts and treat them as a condition of the quoted performance, so a design that departs from the recommended layout has no claim on the data sheet figures, and asking whether the reference design was followed is the standard first question in applications support.[270] Vendors began pushing designs from their online circuit selection tools straight out to PCB packages, which is most useful for switching regulators because their layout is sensitive to high-frequency noise.[203] The recurring vendor vision of modular electronics, in which pre-laid-out functional blocks are dropped into a design so that no custom layout is needed, has been promoted repeatedly without displacing custom layout.[565] A standardised pre-laid-out switching block only transfers between designs if the controller’s behaviour is identical to microsecond accuracy, because any behavioural difference propagates through the rest of the design.[541]
Libraries and footprints
Assigning symbols and footprints for a new design is a distinct phase that precedes layout and can consume around two weeks.[131] Tools differ in when footprint choice is made: Eagle binds a package to each library device variant, whereas Altium and KiCad place only the schematic symbol and defer package assignment to the point of moving into layout, which makes the designer the librarian at that moment.[131] Professional-tier design flows assume a librarian has produced correct part data before schematic capture, giving a siloed sequence of library work, schematic and layout with discrete handoffs, while hobby-oriented tools allow the same decisions to be deferred and made more freely.[131] Where a tool ships few usable footprints, footprint creation can dominate the layout task, taking a reported eighty percent of the time on a design using unfamiliar parts.[29] An IPC footprint generator does not remove footprint work, because many companies mandate the manufacturer’s recommended footprint, their own in-house standard, or the footprint supplied by their assembler in preference to the IPC one.[29] Bad footprints surface as assembly cost rather than design cost, with the assembler spending hours correcting land patterns such as an incorrect 0603 footprint; customers who have built their own prototypes tend to have already found and fixed these.[411]
A widely reported laptop failure was traced to a library error rather than to layout or schematic work: the librarian numbered connector pins so that pin 1 and pin 43 appeared numerically distant while being physically adjacent, allowing a fifty-two volt backlight rail to sit next to a low-voltage differential signal line.[447] Drawing a connector symbol so its pins are grouped to reflect the physical arrangement of the connector, rather than in numerical order, guards against adjacency errors that pin numbering alone conceals.[447]
Unused microcontroller pins can be used as routing feedthroughs: on a densely charlieplexed array of 0201 LEDs with the microcontroller on the reverse side, nets were carried through pins of the device that were not otherwise in use.[697] Marking ground pins with square pads rather than round ones is used as a layout convention that makes a supply net identifiable from the artwork alone.[528] KiCad 7 added a database-backed part library, allowing a librarian role and revision control over parts instead of per-file libraries, along with a scalable bitmap import that lets an existing board photograph be traced over to recreate a layout without any schematic symbols.[621]
Mechanical and assembly constraints
Mechanical depanelling features have to be planned before layout begins: a V-groove encroaches on the board edge by roughly half a millimetre to a millimetre, so a board-level design rule keepout is set at that distance plus an extra millimetre of tolerance and everything is kept inside it.[482] Discovering an edge-clearance problem after routing is complete leaves few options, which is why depanelling and mechanical clearances are decided before layout starts.[482]
Placing a ceramic capacitor close to a mounting screw hole is a layout hazard, because flexing the board while screwing it to a chassis can crack the capacitor and produce a short circuit and a fire.[596] Capacitor terminations with a conductive epoxy sub-metallisation allow a board to flex without a crack propagating into the capacitor body, and such parts are available from multiple manufacturers.[596] Placing a large copper plane under a component that will later need to be desoldered makes rework difficult, because the plane conducts heat away from the joint; this is a placement decision whose cost appears only at rework time.[153]
A design for manufacture review examines layout properties that affect assembly rather than function: whether there is clearance between parts for the pick and place head, and whether parts are on the correct side of the board.[716] Heavy parts on the underside of a board force it through reflow twice and can require re-layout; at quantities of ten or twenty an assembler can jig around the problem, but at around five hundred units design for manufacture constraints become binding.[716] Panelisation can be done by the fabricator’s automatic array-and-rail tool or arranged by the designer; an 18 by 38 millimetre board was placed as a four-by-two array to reach a 70 by 70 millimetre panel with rails added, while spacing boards at the minimum gap leaves dead panel area.[700] Keeping library footprint orientations aligned with the orientation of parts in the pick and place feeders removes a class of assembly error and shortens the path from finished layout to assembled board.[224]
Routing practice
Devices with swappable pin assignments, such as certain microcontrollers, make board layout easier because a pin allocation that routes badly can be changed after placement rather than forcing the traces to conform.[482] Professional tools provide automated fan-out for very large ball grid arrays: with the layer count and design rules defined, the tool escapes the pins outward just beyond the package and produces a reasonable starting point for a device of one thousand five hundred pins.[393] The pin-swap method for a programmable device is to route the surrounding circuitry inward to whichever escaped trace is nearest without connecting it, then run the tool’s pin-swapping function, which pairs each near-touching trace with a pin and joins them; the swaps are recorded as reversible objects so the step can be undone.[393] Automatic pin swapping on a large programmable device cannot be applied blindly, because signals are subject to constraints such as having to fall in a particular quadrant of the device to reach its local quadrant clocks.[393] A large, high pin-count professional board can take a month of layout work even with fan-out and pin-swapping automation available, because the special-case requirements accumulate faster than the tools remove them.[393]
A common working order is to solve the routing problem first and defer footprint detail, on the basis that around ninety percent of a layout can be completed without settled details and the remainder is a tidying step; a wrong footprint is recoverable later unless the pinout itself was mirrored.[219] Once the schematic is finished and parts and footprints are downloaded, routing requires little network access, which makes layout the part of the design flow that can be done offline.[219] Layout is conventionally done with the schematic and the board visible at once on separate screens, on the reasoning that maximum viewing area for both is a working requirement rather than a comfort.[106] Turning off the substrate rendering in a three-dimensional board viewer and looking only at the vias and tracks is a way of building the mental model of how a multi-layer board connects, which is the hardest step for a designer moving from lines on a screen to physical copper.[512]
A power pin left unconnected by the layout produces a board that appears to work but is not robust, a failure class common enough to be recognised on sight.[288] When a circuit misbehaves on a new board, layout is a natural but frequently wrong suspect; building the same device onto an older board of known layout isolates the variable, and a fault that persists across both is not a layout fault.[146]
Autorouting and automated layout
Autorouters are used selectively rather than for a whole board, the working combination being the human designer plus the autorouter applied to specific regions.[219] The niche in which autorouting pays is a block of purely digital nets with no length or matching requirements; outside that, setting up the autorouter correctly takes as long as routing the section by hand.[412] A commercial automated layout service offered in 2018 quoted three thousand dollars for a board in twenty-four hours within stated limits of roughly fifty components, twenty unique parts, three amps, five hundred megahertz and twenty watts, a scope that omits the iteration a prototype normally undergoes.[412]
Automated layout that starts from a schematic treats the board as a compilation target: the constraints taken as input are mechanical ones such as board size and connector positions, while the placement of ordinary integrated circuits, passives and traces is left to the tool under the sole constraint that the result works.[626] An automated layout engine can be run over a partially hand-laid board, leaving regions the designer has laid out untouched and routing around them, a mode used when a customer cares about specific sections such as a vendor-recommended switching regulator layout.[626] One implementation normalises the input by deleting all existing copper and reducing the board to two layers, then branches into two-layer and four-layer variants, generating and calculating the plane pours itself.[626] Automated layout results were validated by re-laying out open-source boards including an Arduino Uno, a stepper motor driver, an MP3 player and a machine vision camera board, buying the originals and testing the generated versions, with a commitment that no human touched the output.[626] On a reduced-density version of a machine vision camera board, an engineer with more than twenty years of layout experience took a day or two while the automated system finished in under an hour; customer boards estimated at two to four engineer days were also produced in about an hour.[626]
Layout in the development process
Board layout tends to sit at the tail end of a hardware programme, after actuators, sensors and mechanical constraints are settled, which makes it a critical path item and delays the point at which the design can be tested in physical form.[626] Under severe time pressure the schematic can be removed from the critical path altogether: a board layout and its components are the irreducible requirements, and the bill of materials can be exported from the layout, since component type and value are already held there.[224] For designs such as large multiplexed LED arrays, the net assignment is determined by the physical arrangement rather than the other way round, so the work necessarily starts from the layout and derives which devices connect to which drivers.[224]
Concentrating layout in one person or one department produces consistency: shared libraries, consistent layout technique, consistent bed-of-nails test point practice, and reuse of parts already held in inventory.[195] The counter-argument to a dedicated layout group is that having one engineer carry a project from schematic through layout removes handoffs, a structure adopted by organisations that value turnaround over layout optimisation.[157] Contract manufacturers commonly do not lay out boards in house and subcontract layout work along with enclosure design, since their specialisation is assembly.[114] Handing a design to a separate layout engineer loses information that is not captured in the netlist, such as which device pins may be reassigned, leaving the designer dependent on the layout engineer reading the accompanying notes.[549]
Board layout engineers are brought into silicon programmes before tape-out so that the ballout can be checked for routability, because a pinout optimised for the die can produce a package that cannot be escaped on a printed circuit board.[452] Pinouts are sometimes still unfinalised when a board design must begin, because bonding decisions can be deferred late in a compressed silicon schedule; the review sequence that contains the resulting risk is schematic review followed by layout review.[452] On the Raspberry Pi Pico programme, the chip pinout and the board layout were co-designed so that pin ordering suited both the module and other users’ boards; the result is a cost-engineered two-layer board with single-sided surface-mount assembly and a dual in-line form factor.[529]
Simultaneous multi-user PCB layout was implemented commercially and worked technically, but is reported to be essentially unused, because splitting a design between people adds interface overhead that is only amortised on teams of roughly five or more engineers.[336] Collaborative layout with two engineers at different companies each taking half of the same board was being practised as early as the mid-1990s.[230] Before hardware version control was available, long layouts were protected by dated subdirectory snapshots taken several times a day and specifically before any strategic change such as a re-route or a large placement move, a discipline that made four- to six-month layouts recoverable.[317] Layout changes are made reviewable by committing them in functional blocks with descriptive messages, so that a graphical difference shows a bounded region such as the power supply area rather than the whole board changing at once.[505]
History
Before computer-aided design, layouts were taped by hand on a light box using rolls of adhesive tape for tracks and pre-printed stick-down pad patterns for packages such as a 16-pin dual in-line device, cut with a knife; the routing term rip-up-and-retry is a direct description of physically removing and re-laying that tape.[128] Dense professional artwork was often taped at twice final size and photographically reduced, which improved the achievable precision relative to hand-cut tape.[106] Board fabrication historically used negative photoresist, so artwork taped up by hand had to be photographically converted to a negative before it could expose the panel, making artwork generation a two-step process.[434] Some fabricators refused artwork containing right-angle track corners outright, so trace geometry conventions were once enforced at the fabrication house rather than by design rule checking.[494]
The cost barrier to board design collapsed over three decades: layout software that cost about five thousand dollars in the 1980s has free equivalents, and prototype fabrication that carried around a thousand dollars of setup cost is available for tens of dollars.[167] The standard open-source flow runs schematic capture, then a step tying schematic symbols to footprints, then module placement, routing, and export of fabrication files.[167] Browser-based electronic design tools moved from schematic sharing into board layout around 2012, with Upverter adding layout and export toward established CAD formats and Circuits.io appearing at the same time.[122] Scripted board generation, in which placement information and a board outline file are supplied as inputs and the artwork is emitted as vector output, exists as an alternative to interactive layout.[130]
Effort, skill and practice
Layout duration scales sharply with complexity: a simple microcontroller board of Arduino size can be laid out in a day or hours, an experienced designer typically reaches the layout stage within a couple of days of starting a design, and an advanced multi-page design can take one to two months of schematic work followed by two to four months of layout.[470] For an advanced board developed as a teaching reference, the schematic ran to many pages and required one to two months, and the layout took between two and four months depending on board size and difficulty.[316] Individual layouts of six months are recorded for very intricate single-board designs; the driver is the intricacy and the decision to put everything on one board rather than the layer count alone, though high layer counts accompany such designs.[316] On a large design the routing effort is set by the total pin count that must be connected, a schematic of around fifty dense pages cannot be laid out in weeks, and re-routing after being boxed into a corner remains expensive even with push-and-shove routing available.[316] A rough working split for a modest board is a day of schematic and bill of materials work followed by at least a day of layout, giving two full working days as the minimum realistic figure.[127] A month spent on a single layout is used as the informal threshold for having encountered a genuinely complex board.[574] Quoting layout work is done by experience: an experienced layout engineer working from a completed schematic can estimate the job accurately and may hold a standard rate, while unfamiliar parts justify additional padding.[70]
Layout is treated as a skill requiring sustained deliberate practice on the order of the ten-thousand-hour scale, developed by repetition on real projects finished end to end rather than by reading.[669] Layout speed and efficiency decay when the work is not done daily, though the underlying capability is retained and recovery is estimated in days or weeks.[342] Layout requires long uninterrupted blocks, because reloading the mental state of a partially placed board is expensive; practitioners describe needing half a day rather than ten minutes to enter layout work, and a scheme allotting a few hours a week to a hardware project is reported not to work for this reason.[564] Interruption in the middle of a layout is described as costing most of a working day.[82]
In teaching layout, the board routing is deliberately withheld from students while schematic files and part libraries are supplied, because deciding via placement and trace widths for oneself is the part that transfers and watching it done does not.[573] Beginners are advised to build layout skill on two-layer boards and on the specific technique currently being learned, rather than measuring themselves against an eight-layer design.[436] Teaching layout to a group is far slower than doing it: a structured online course took around six weeks to reach the layout stage, covering part selection and footprint association first.[186] Tearing down an existing product and reverse engineering it to schematic and component values is used as a route into layout judgment, because it exposes the trade-offs behind component selection and physical arrangement that first-principles teaching omits.[119] Time spent placing and routing a design is what builds the mental model of how the circuit works, and that model is what makes later hard debugging possible; a layout delegated entirely to a tool leaves the engineer without it.[722] Free and professional PCB packages are separated by efficiency rather than capability: boards of any complexity can be completed in a free tool, but tooling support thins out as complexity rises, so the paid seat buys time rather than reach.[574]